-64-
Pin Function Name
Function
Pol.
Action
16 TEMP_LED_EX
Temp. LED Drive
O
L: On, H: Off
17 LAMP_REP_LED_EX
Lamp Replace LED Drive
O
L: On, H: Off
18 PJ_UPDATE_EX
Write Forcely for PJ-Net Board
O
L: Write
19 (Not used)
I
20 (Not used)
I
21 W-SW
Wired RC Detection
I
L: Wired RC Connected
22 CPU_CHK_DPRAM
INT Clear
I
L:not INT Clear
23 S3.3V
-
-
24 X1
(Not used)
I
H Fixed
25 GND
-
-
26 X2
(Not used)
O
Open
27 A0
Address 0
I
-
28 A1
Address 1
I
-
29 A2
Address 2
I
-
30 A3
Address 3
I
-
31 A4
Address 4
I
-
32 CLOCK
Clock Input(9.8304MHz)
I
-
33 S3.3V
-
-
34 RC_CTRL_0
Selects Rear RC Receiver
O
L: Rear RC
35 RC_CTRL_1
Selects Front RC Receiver
O
L: Front RC
36 FPGA_HZ
FPGA Hi-Z (DRAM Reset)
O
H after configuration
37 SH_BSY
Prohibit DRAM Access at Same time
O
L: Busy
38 D0
Data Bus 0
B
-
39 D1
Data Bus 1
B
-
40 D2
Data Bus 2
B
-
41 D3
Data Bus 3
B
-
42 GND
-
-
43 RD
Read Signal
I
-
44 CS6_IOEXP
Chip Enable
I
-
45 WE0
Write Signal
I
-
46 LENS_TOP
Detection for Top Limit Position of Lens
I
L: Limit on
47 LENS_BOT
Detection for Bottom Llimit Position of Lens
I
L: Limit on
48 PRODUCT_OPT1
Product Option
I
49 PRODUCT_OPT2
Product Option
I
50 FOCUS+_EX
Focus Up
O
L: Active, H: Stop
51 FOCUS-_EX
Focus Down
O
L: Active, H: Stop
52 GND
-
-
53 ZOOM+_EX
Zoom Up
O
L: Active, H: Stop
54 ZOOM-_EX
Zoom Down
O
L: Active, H: Stop
55 S3.3V
-
-
56 S3.3V
-
-
57 MODE0
Mode Select
I
L fixed
58 MODE1
Mode Select
I
L fixed
59 DEV0
Division Signal
I
Switch (Initial:L)
60 DEV1
Division Signal
I
Switch (Initial:L)
61 GND
-
-
62 EXP_RESET
Reset Input Signal
I
H Reset
63 GND
-
-
64 S3.3V
Analog Power
-
-
65 (Not used)
AI
66 (Not used)
AI
67 (Not used)
AI
68 (Not used)
AI
69 (Not used)
AO
70 GND
Analog Ground
-
-
71 Select
Clock Select
I
H Fixed
72 GND
-
-
73 S3.3V
-
-
74 D4
Data Bus 4
B
-
75 D5
Data Bus 5
B
-
76 D6
Data Bus 6
B
-
77 D7
Data Bus 7
B
-
78 (Reserved)
Serial Port Wakeup
O
(Open)
79 IRQ5
Interrupt Output(Level Output)
O
-
80
Serial Port Invalid
I
(Open)
Control Port Functions
Summary of Contents for PLV-80 Series
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