53
Frame Relay for Sangoma Cards (C) Sangoma Technologies Inc. 1999,2000,2001 Page 53 of 78
bit 3 - the ‘command complete’ interrupt bit.
If bit 3 is set, then an interrupt will be triggered on completion of an interface
command, i.e. when the 'opp_flag' has been reset.
bit 4 - the channel/DLCI status interrupt bit.
If bit 4 is set, then an interrupt will be triggered on a change in status of the
channel or a DLCI. The details of this status change may be established by
using an READ_DLC_STATUS command to illicit a return code of 0x11,
0x12, 0x13 or 0x14 as documented in the section "Notes on Return Codes and
Status Bytes".
bits 5, 6, 7 - reserved for later use.
Offset 0x01-0x02: (only applicable when enabling transmit interrupts in the
DLCI-specific mode) - the length of the outgoing frame for which a transmit
interrupt should be triggered. Note that this parameter is represented by a two
byte, unsigned short variable.
DLCI:
used in conjunction with transmit interrupts and is set to zero to enable non DLCI
specific interrupts or to a specific DLCI on which the Information frame is to be
transmitted.
Control Block values set on return:
RETURN_
CODE:
0x00 The action has been performed successfully.
0x04
(only applicable when enabling transmit interrupts) - the DLCI selected is
invalid (i.e., it was not included in the DLCIs listed in the
SET_DLCI_CONFIGURATION command).
0x05
(only applicable when enabling transmit interrupts) - the length of the frame to
be transmitted exceeded the maximum I-frame length defined by the
SET_DLCI_CONFIGURATION command.
