CP3005 – User Guide Rev. 1.8
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4.3.13.
Board ID Low-Byte Register (BIDL)
Table 31: Board ID Low-Byte Register (BIDL)
Address
0x28D
Bit
7
6
5
4
3
2
1
0
Name
BIDL
R
0x80
Access
Reset
Bitfield
Description
7 - 0
BIDL
Board identification:
CP3005: 0xB480
The Board ID High Byte Register is located at the address 0x288.
4.3.14.
LED Configuration Register (LCFG)
The LED Configuration Register holds a series of bits defining the onboard configuration for the front panel General
Purpose LEDs.
Table 32: LED Configuration Register (LCFG)
Address
0x290
Bit
7
6
5
4
3
2
1
0
Name
Reserved
LCON
Access
R
R/W
Reset
0000
0000
Bitfield
Description
3 - 0
LCON
LED3..0 configuration:
0000 = POST Mode (LEDs build a binary vector to display the Port 80
value)
0001 = General Purpose Mode (LEDs are controlled via the LCTRL
register)
0010 - 1111 = Reserved
Beside the configurable functions described above, LED3..0 fulfill also a basic debug function
during the power-up phase as long as the first access to Port 80 is processed. For further
information on reading the 8-bit uEFI BIOS POST Code, refer to section 0.
