CP3005 – User Guide Rev. 1.8
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Sub-Screen
Function
Description
Jitter Error Target
VOC Dwell Time
VOC Error Target
Generate BDAT PEG Margin
Data
PCIe Rx CEM Test Mode
PCI Spread Spectrum
Clocking
2
10000
2
[Enabled/Disabled]
[Enabled/Disabled]
[Enabled/Disabled]
PCH-IO
Configuration
SATA and RST
Configuration
SATA Controller
[Enabled/Disabled]
SATA Mode Selection
[AHCI]
SATA Controller Speed
[Auto]
Software Feature Mask
HDD Unlock
[Enabled]
LED Locate
[Enabled]
Port 4
[Enabled]
Spin Up Device
[Disabled]
SATA Device Type
[Solid State Drive]
USB Configuration
xDCI Support
[Disabled]
USB PHY Sus Well Power
Gating
[Enabled]
USB2.0 Port1 Front Panel
(lower)
[Enabled]
USB2.0 Port8 WIBU
[Enabled]
USB2.0 Port9 Front Panel
(upper)
[Enabled]
Security Configuration
RTC Memory Clock
[Disabled]
BIOS Lock
[Disabled]
Force Unlock on all GPIO
Pads
[Disabled]
HD Audio Configuration
HD Audio
[Disabled]
PCH LAN Controller
LAN Wake From DeepSx
Wake on LAN Enable
SLP_LAN# Low on DC
Power
State after G3
[Enabled/Disabled]
[Enabled/Disabled]
[Enabled/Disabled]
[Enabled/Disabled]
[S0 State]