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INTERRUPT STRUCTURE

S3C8248/C8245/P8245/C8247/C8249/P8249

5-10

INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required
settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit
of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a
level's IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions
using the Register addressing mode.

Interrupt Mask Register (IMR)

DDH, Set 1, R/W

.7

.6

.5

.4

.3

.2

.1

.0

MSB

LSB

IRQ1

IRQ2

IRQ4

IRQ5

IRQ6

IRQ7

IRQ0

Interrupt level enable bits (7-4, 2-0)
0 = Disable (mask) interrupt level
1 = Enable (un-mask) interrupt level

IRQ3

NOTE:

Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.

Figure 5-6. Interrupt Mask Register (IMR)

Summary of Contents for C8245

Page 1: ...23 S3 C8248 C8245 P8245 C8247 C8249 P8249 032002 USER S MANUAL S3C8248 C8245 P8245 C8247 C8249 P8249 8 Bit CMOS Microcontrollers Revision 3 ...

Page 2: ...me programmable ROM embedded The S3P8249 is a microcontroller with a 32K byte one time programmable ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C8248 C8245 P8245 C8247 C8249 P8249 by integrating the following peripheral modules with the powerful SAM8 core Six programmable I O ports including five 8 bit ports and one 5 bit port for a total...

Page 3: ...ch interrupt generates 16 Bit Timer Counter 1 Programmable 16 bit timer Interval capture PWM mode Match capture overflow interrupt Watch Timer Real time and interval time measurement Clock generation for LCD Four frequency outputs for buzzer sound LCD Controller Driver Maximum 16 digit LCD direct drive capability Display modes static 1 2 duty 1 2 bias 1 3 duty 1 2 or 1 3 bias 1 4 duty 1 3 bias A D...

Page 4: ...0 I O Port 1 A D Converter I O Port 2 8 Bit Timer Counter A I O Port 3 TAOUT TAPWM P3 1 TACLK P3 2 TACAP P3 3 TBPWM P3 0 T1CAP P1 0 T1CLK P1 1 T1OUT T1PWM P1 2 P0 0 P0 7 INT0 INT7 P1 0 P1 7 AVREF AVSS P2 0 P2 7 ADC0 ADC7 LCD Driver Serial I O Port P3 0 P3 4 Voltage Detector VVLDREF I O Port 5 I O Port 4 Voltage Booster CB CA VLC0 VLC2 COM0 COM3 SEG0 SEG15 SEG16 SEG31 SI P1 7 SO P1 5 SCK P1 6 P4 0 ...

Page 5: ...4 INT4 S3C8248 C8245 C8247 C8249 80 QFP 1420C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 CA CB AVSS AVREF P2 7 ADC7 VVLDREF P2 ...

Page 6: ...C8249 80 TQFP 1212 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 CA CB AVSS AVREF P2 7 ADC7 VLDREF P2 6 ADC6 P2 5 ADC5 P0 1 INT1 P0 2 INT2 P0 3 INT3 P...

Page 7: ... assignable pull up Alternately P1 0 P1 7 can be used as SI SO SCK BUZ T1CAP T1CLK T1OUT T1PWM E 2 28 35 SI SO SCK BUZ T1CAP T1CLK T1OUT T1PWM P2 0 P2 7 I O I O port with bit programmable pins normal input and AD input or output mode selected by software software assignable pull up F 10 F 18 36 42 43 ADC0 ADC6 VVLDREF ADC7 P3 0 P3 4 I O I O port with bit programmable pins Input or push pull output...

Page 8: ... 13 XOUT XIN Main oscillator pins 14 15 SCK SO SI I O Serial I O interface clock signal E 2 33 35 P1 5 P1 7 VVLDREF I Voltage detector reference voltage input F 18 43 P2 7 TACAP I Timer A Capture input D 2 10 P3 3 TACLK I Timer A External clock input D 2 9 P3 2 TAOUT TAPWM O Timer A output and PWM output D 2 8 P3 1 TBPWM O Timer B PWM output D 2 7 P3 0 T1CAP I Timer 1 Capture input E 2 28 P1 0 T1C...

Page 9: ...SET P Channel N Channel VDD Out Output Disable Data Figure 1 5 Pin Circuit Type C P Channel I O Output Disable Data Circuit Type C Pull up Enable VDD Figure 1 6 Pin Circuit Type D 2 P3 I O Output Disable Data Pin Circuit Type C Pull up Enable VDD Noise Filter Ext INT Input Normal VDD Figure 1 7 Pin Circuit Type D 4 P0 ...

Page 10: ...gure 1 8 Pin Circuit Type E 2 P1 Pull up Enable Circuit Type C Data Output Disable ADCEN To ADC Data VDD I O Figure 1 9 Pin Circuit Type F 10 P2 0 P2 6 Pull up Enable Circuit Type C Data Output Disable ADC VLD Enable Data To ADC VLDREF I O VDD Figure 1 10 Pin Circuit Type F 18 P2 7 VLDREF Out VLC1 SEG COM VLC0 VLC2 Figure 1 11 Pin Circuit Type H SEG COM ...

Page 11: ...245 P8245 C8247 C8249 P8249 1 10 SEG VLC2 VLC1 VLC0 Output Disable Figure 1 12 Pin Circuit Type H 4 VDD Open Drain EN Data LCD Out EN SEG Output Disable Pull up Enable VDD Circuit Type H 4 Figure 1 13 Pin Circuit Type H 14 P4 P5 ...

Page 12: ...n internal 32 Kbyte mask programmable ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes A 16 byte LCD display register file is implemented There are 1 109 mapped registers in the internal register file Of these 1 040 are for general purpose This number includes a 16 byte working register common area used as a scratch area for data ope...

Page 13: ... for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal 32 767 255 HEX 7FFFH S3C8249 0FFH 0H 0 Interrupt Vector Area 32K byte 3FFFH...

Page 14: ...r can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SB0 and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C8247 ...

Page 15: ... DFH D0H CFH C0H Prime Data Registers All addressing modes LCD Display Reigster Page 4 0FH 00H 16 Bytes Page 1 Page3 Page 2 Page 1 Page 0 Prime Data Registers All Addressing Modes Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations C0H BFH 00H FFH FFH FFH FFH 192 Bytes 64 Bytes 256 Bytes NOTE In case of S3C8248 C8245 P8245 there are page 0 page 1 and pag...

Page 16: ... 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W LSB MSB 7 6 5 4 3 2 1 0 Destination register page selection bits 0000 Destination Page 0 Source register page selection bits 0000 Source Page 0 NOTE A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to ...

Page 17: ...egisters in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations C0H FFH is logically duplicated to ad...

Page 18: ...area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 1 2 3 or 4 you must set the register page pointer PP to the appropriate source and destination values FFH FCH E0H D0H C0H Set 1 Bank 0 Peripheral and I O General purpose CPU and system control LCD data register FFH Page 3 Set 2 FFH Page 2 Set 2 FFH Page 1 Set 2 FFH C0H 00H BFH Page 0 Set 2 Pa...

Page 19: ...and relative locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to p...

Page 20: ... modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RP0 point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RP0 points to the upper slice...

Page 21: ...DD R0 R1 R0 R0 R1 ADC R0 R2 R0 R0 R2 C ADC R0 R3 R0 R0 R3 C ADC R0 R4 R0 R0 R4 C ADC R0 R5 R0 R0 R5 C The sum of these six registers 6FH is located in the register R0 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence wou...

Page 22: ...ter file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the leas...

Page 23: ...5 C8247 C8249 microcontroller pages 0 4 are implemented Pages 0 4 contain all of the addressable registers in the internal register file Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RP0 points to locations C0H C7H and RP1 to locations C8H CFH that is to the common working register area FFH C0H Set 2 Prime Regist...

Page 24: ...an be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages FFH Page 3 Set 2 FFH Page 2 Set 2 FFH Page 1 Set 2 FFH C0H 00H BFH Page 0 Set 2 Page 0 Prime Space LCD Data Registers Page 4 00H 0FH FFH FCH E0H D0H C0H Set 1 Following a hardware reset regi...

Page 25: ...ister area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RP0 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown ...

Page 26: ... high order bits Address OPCODE Selects RP0 or RP1 RP1 RP0 4 bit address provides three low order bits Figure 2 11 4 Bit Working Register Addressing Register address 76H RP0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 R6 0 1 1 0 1 1 1 0 Selects RP0 Instruction INC R6 OPCODE RP1 0 1 1 1 1 0 0 0 Figure 2 12 4 Bit Working Register Addressing Example ...

Page 27: ...of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 0...

Page 28: ...CES 2 17 8 bit address form instruction LD R11 R2 RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address 0ABH RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2 14 8 Bit Working Register Addressing Example ...

Page 29: ...Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and t...

Page 30: ...n the internal register file using PUSH and POP instructions LD SPL 0FFH SPL FFH Normally the SPL is set to 0FFH by the initialization routine PUSH PP Stack address 0FEH PP PUSH RP0 Stack address 0FDH RP0 PUSH RP1 Stack address 0FCH RP1 PUSH R3 Stack address 0FBH R3 POP R3 R3 Stack address 0FBH POP RP1 RP1 Stack address 0FCH POP RP0 RP0 Stack address 0FDH POP PP PP Stack address 0FEH ...

Page 31: ...ADDRESS SPACES S3C8248 C8245 P8245 C8247 C8249 P8249 2 20 NOTES ...

Page 32: ...ed to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R...

Page 33: ... Execution OPCODE OPERAND 8 bit Register File Address Point to One Register in Register File One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Program Memory Register File Figure 3 1 Register Addressing dst OPCODE 4 bit Working Register Point to the Working Register 1 of 8 Two Operand Instruction Example Sample Instruction ADD R1 R2 Wh...

Page 34: ... bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations C0H FFH in set 1 using the Indirect Register addressing mode dst Address of Operand used by Instruction OPCODE ADDRESS 8 bit Register File Address Point to One Register in Register File One Operand Instruction E...

Page 35: ...st OPCODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions CALL RR2 JP RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16 Bit Address Points to Program Memory Figure 3 4 Indirect Register Addressing to Program Memory ...

Page 36: ...4 bit Working Register Address Point to the Working Register 1 of 8 Sample Instruction OR R3 R6 Program Memory Register File src 3 LSBs Value used in Instruction OPERAND Selected RP points to start fo working register block RP0 or RP1 MSB Points to RP0 or RP1 Figure 3 5 Indirect Working Register Addressing to Register File ...

Page 37: ...ry access Program Memory Register File src Value used in Instruction OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2 bit Point to Working Register Pair 1 of 4 LSB Selects Register Pair 16 Bit address points to program memory or data memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Figur...

Page 38: ...struction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction...

Page 39: ...ed RP points to start of working register block dst src OPCODE Program Memory x OFFSET 4 bit Working Register Address Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 2 Bits Register Pair Value used in Instruction 8 Bits 16 Bits 16 Bits Figu...

Page 40: ... RP points to start of working register block Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 2 Bits Register Pair Value used in Instruction 8 Bits 16 Bits 16 Bits dst src OPCODE Program Memory src OFFSET 4 bit Working Register Addres...

Page 41: ...ct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed dst src OPCODE Program Memory 0 or 1 Lower Address Byt...

Page 42: ...inued OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Next OPCODE Figure 3 11 Direct Addressing for Call and Jump Instructions ...

Page 43: ...irect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Current Instruction Program Memory Locations 0 255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must be Z...

Page 44: ... addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions JR ULT OFFSET Where OFFSET...

Page 45: ...ion is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers The Operand value is in the instruction OPCODE Sample Instruction LD R0 0AAH Program Memory OPERAND Figure 3 14 Immediate Addressing ...

Page 46: ...n the corresponding peripheral descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S3C8248 C8245 C8247 C8249 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Register Name Mnemonic Decimal Hex R W LCD control register LCON 20...

Page 47: ... B data register low byte TBDATAL 235 EBH R W Timer B control register TBCON 236 ECH R W Timer A control register TACON 237 EDH R W Timer A counter register TACNT 238 EEH R Timer A data register TADATA 239 EFH R W Serial I O control register SIOCON 240 F0H R W Serial I O data register SIODATA 241 F1H R W Serial I O pre scale register SIOPS 242 F2H R W Oscillator control register OSCCON 243 F3H R W...

Page 48: ...F2H R Timer 0 counter register low byte T0CNTL 243 F3H R Timer 0 data register high byte T0DATAH 244 F4H R W Timer 0 data register low byte T0DATAL 245 F5H R W Voltage level detector control register VLDCON 246 F6H R W A D converter control register ADCON 247 F7H R W A D converter data register high byte ADDATAH 248 F8H R W A D converter data register low byte ADDATAL 249 F9H R W Watch timer contr...

Page 49: ...ng Name of individual bit or related bits Register name Register ID Sign Flag S 0 Operation does not generate a carry or borrow condition 0 Operation generates carry out or borrow into high order bit 7 0 Operation result is a non zero value 0 Operation result is zero 0 Operation generates positive number MSB 0 0 Operation generates negative number MSB 1 Description of the effect of specific bit se...

Page 50: ...ssing Mode Register addressing mode only 7 Not used for the S3C8248 C8245 C8247 C8249 6 4 A D Input Pin Selection Bits 0 0 0 ADC0 0 0 1 ADC1 0 1 0 ADC2 0 1 1 ADC3 1 0 0 ADC4 1 0 1 ADC5 1 1 0 ADC6 1 1 1 ADC7 3 End of Conversion bit read only 0 Conversion not complete 1 Conversion complete 2 1 Clock Source Selection Bits 0 0 fxx 16 0 1 fxx 8 1 0 fxx 4 1 1 fxx 0 Start or Enable Bit 0 Disable operatio...

Page 51: ... 0 1 fxx 1024 1 0 fxx 128 1 1 fxx 16 1 Basic Timer Counter Clear Bit 1 0 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer Counters 2 0 No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automat...

Page 52: ...Addressing Mode Register addressing mode only 7 5 Not used for the S3C8248 C8245 C8247 C8249 4 3 CPU Clock System Clock Selection Bits note 0 0 fxx 16 0 1 fxx 8 1 0 fxx 2 1 1 fxx 2 0 Not used for the S3C8248 C8245 C8247 C8249 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ...

Page 53: ...8245 C8247 C8249 P8249 4 8 EMT External Memory Timing Register FEH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET RESET Value 0 Read Write Addressing Mode Register addressing mode only 7 0 Not used for the S3C8248 C8245 C8247 C8249 ...

Page 54: ...zero 5 Sign Flag S 0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 Decimal Adjust Flag D 0 Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H 0 No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry...

Page 55: ...k 5 Interrupt Level 5 IRQ5 Enable Bit Watch Timer Overflow 0 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Enable Bit SIO Interrupt 0 Disable mask 1 Enable unmask 3 Interrupt Level 3 IRQ3 Enable Bit Timer 1 Match Capture or Overflow 0 Disable mask 1 Enable unmask 2 Interrupt Level 2 IRQ2 Enable Bit Timer 0 Match 0 Disable mask 1 Enable unmask 1 Interrupt Level 1 IRQ1 Enable Bit Timer B Mat...

Page 56: ...he S3C8248 C8245 C8247 C8249 2 Timer 1 Overflow Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 Timer 1 Match Capture Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 Timer A Overflow Interrupt Pending bit 0 Interrupt request is not pending pending bit cl...

Page 57: ...per eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL Instruction Pointer Low Byte DBH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction poi...

Page 58: ...rupt Groups A B and C 0 0 0 Group priority undefined 0 0 1 B C A 0 1 0 A B C 0 1 1 B A C 1 0 0 C A B 1 0 1 C B A 1 1 0 A C B 1 1 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 IRQ7 1 IRQ7 IRQ6 5 Interrupt Group C Priority Control Bit 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 3 Interrupt Subgroup B Priority Control Bit 0 IRQ3 IRQ4 1 IRQ4 IRQ3 2 Interrupt Group B Priority Cont...

Page 59: ...t Pending Bit External Interrupts P0 0 0 3 0 Not pending 1 Pending 5 Level 5 IRQ5 Request Pending Bit Watch Timer Overflow 0 Not pending 1 Pending 4 Level 4 IRQ4 Request Pending Bit SIO Interrupt 0 Not pending 1 Pending 3 Level 3 IRQ3 Request Pending Bit Timer 1 Match Capture or Overflow 0 Not pending 1 Pending 2 Level 2 IRQ2 Request Pending Bit Timer 0 Match 0 Not pending 1 Pending 1 Level 1 IRQ1...

Page 60: ... I O is selected 1 SEG20 EG23 is selected P4 4 P4 7 I O is disabled 4 LCD Output Segment and Pin Configuration Bits 0 P4 0 P4 3 I O is selected 1 SEG16 SEG19 is selected P4 0 P4 3 I O is disabled 3 Not used for the S3C8248 C8245 C8247 C8249 2 LCD Bias Voltage Selection Bit 0 Enable LCD initial circuit internal bias voltage 1 Disable LCD initial circuit for external LCD driving resister external bi...

Page 61: ...the S3C8248 C8245 C8247 C8249 5 4 LCD Clock LCDCK Frequency Selection Bits 0 0 32 768 kHz watch timer clock fw 29 64 Hz 0 1 32 768 kHz watch timer clock fw 28 128 Hz 1 0 32 768 kHz watch timer clock fw 27 256 Hz 1 1 32 768 kHz watch timer clock fw 26 512 Hz 3 0 Duty and Bias Selection for LCD Display 0 x x x LCD display off COM and SEG output low 1 0 0 0 1 4 duty 1 3 bias 1 0 0 1 1 3 duty 1 3 bias...

Page 62: ...Sub system Oscillator Driving Ability Control Bit 0 Strong driving ability 1 Normal driving ability 3 Main System Oscillator Control Bit 0 Main System Oscillator RUN 1 Main System Oscillator STOP 2 Sub System Oscillator Control Bit 0 Sub system oscillator RUN 1 Sub system oscillator STOP 1 Not used for the S3C8248 C8245 C8247 C8249 0 System Clock Selection Bit 0 Main oscillator select 1 Subsystem ...

Page 63: ...push pull 5 4 P0 6 INT6 0 0 Schmitt trigger input mode pull up interrupt on falling edge 0 1 Schmitt trigger input mode interrupt on rising edge 1 0 Schmitt trigger input mode interrupt on rising or falling edge 1 1 Output mode push pull 3 2 P0 5 INT5 0 0 Schmitt trigger input mode pull up interrupt on falling edge 0 1 Schmitt trigger input mode interrupt on rising edge 1 0 Schmitt trigger input m...

Page 64: ...ush pull 5 4 P0 2 INT2 0 0 Schmitt trigger input mode pull up interrupt on falling edge 0 1 Schmitt trigger input mode interrupt on rising edge 1 0 Schmitt trigger input mode interrupt on rising or falling edge 1 1 Output mode push pull 3 2 P0 1 INT1 0 0 Schmitt trigger input mode pull up interrupt on falling edge 0 1 Schmitt trigger input mode interrupt on rising edge 1 0 Schmitt trigger input mo...

Page 65: ... External Interrupt INT6 Enable Bit 0 Disable interrupt 1 Enable interrupt 5 P0 5 External Interrupt INT5 Enable Bit 0 Disable interrupt 1 Enable interrupt 4 P0 4 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 3 P0 3 External Interrupt INT3 Enable Bit 0 Disable interrupt 1 Enable interrupt 2 P0 2 External Interrupt INT2 Enable Bit 0 Disable interrupt 1 Enable interrupt 1...

Page 66: ...ding Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 P0 4 INT4 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 3 P0 3 INT3 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P0 2 INT2 Interrupt Pending Bi...

Page 67: ...e only 7 6 P1 7 SI 0 0 Input mode SI 0 1 Output mode open drain 1 0 Alternative function push pull output 1 1 Output mode push pull 5 4 P1 6 SCK 0 0 Input mode SCK 0 1 Output mode open drain 1 0 Alternative function SCK out 1 1 Output mode push pull 3 2 P1 5 SO 0 0 Input mode 0 1 Output mode open drain 1 0 Alternative function SO 1 1 Output mode push pull 1 0 P1 4 BUZ 0 0 Input mode 0 1 Output mod...

Page 68: ...0 1 Output mode open drain 1 0 Alternative function push pull output mode 1 1 Output mode push pull 5 4 P1 2 T1OUT T1PWM 0 0 Input mode 0 1 Output mode open drain 1 0 Alternative function T1OUT T1PWM 1 1 Output mode push pull 3 2 P1 1 T1CLK 0 0 Input mode T1CLK 0 1 Output mode open drain 1 0 Alternative function push pull output mode 1 1 Output mode push pull 1 0 P1 0 T1CAP 0 0 Input mode T1CAP 0 ...

Page 69: ... disable 1 Pull up enable 6 P1 6 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 5 P1 5 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 4 P1 4 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 3 P1 3 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 2 P1 2 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 1 P1 1 Pull up Resistor ...

Page 70: ...de only 7 6 P2 7 VLDREF ADC7 0 0 Input mode 0 1 Input mode pull up 1 0 Alternative function ADC VLD mode 1 1 Output mode push pull 5 4 P2 6 ADC6 0 0 Input mode 0 1 Input mode pull up 1 0 Alternative function ADC mode 1 1 Output mode push pull 3 2 P2 5 ADC5 0 0 Input mode 0 1 Input mode pull up 1 0 Alternative function ADC mode 1 1 Output mode push pull 1 0 P2 4 ADC4 0 0 Input mode 0 1 Input mode p...

Page 71: ...ng mode only 7 6 P2 3 ADC3 0 0 Input mode 0 1 Input mode pull up 1 0 Alternative function ADC mode 1 1 Output mode push pull 5 4 P2 2 ADC2 0 0 Input mode 0 1 Input mode pull up 1 0 Alternative function ADC mode 1 1 Output mode push pull 3 2 P2 1 ADC1 0 0 Input mode 0 1 Input mode pull up 1 0 Alternative function ADC mode 1 1 Output mode push pull 1 0 P2 0 ADC0 0 0 Input mode 0 1 Input mode pull up...

Page 72: ...gh Byte E8H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 2 Not used for the S3C8248 C8245 C8247 C8249 1 0 P3 4 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 x Output mode push pull ...

Page 73: ... 0 0 Input mode TACAP 0 1 Input mode pull up TACAP 1 0 Output mode push pull 1 1 Output mode push pull 5 4 P3 2 TACLK Mode Selection Bits 0 0 Input mode TACLK 0 1 Input mode pull up 1 0 Output mode push pull 1 1 Output mode push pull 3 2 P3 1 TAOUT TAPWM Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Alternative function TAOUT or TAPWM 1 1 Output mode push pull 1 0 P3 0 TBPWM Mode S...

Page 74: ...Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 5 4 P4 6 SEG22 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 3 2 P4 5 SEG21 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 1 0 P4 4 SEG20 Mode Selection Bits 0 ...

Page 75: ...Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 5 4 P4 2 SEG18 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 3 2 P4 1 SEG17 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 1 0 P4 0 SEG16 Mode Selection Bits 0 ...

Page 76: ...Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 5 4 P5 6 SEG30 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 3 2 P5 5 SEG29 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 1 0 P5 4 SEG28 Mode Selection Bits 0 ...

Page 77: ...Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 5 4 P5 2 SEG26 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 3 2 P5 1 SEG25 Mode Selection Bits 0 0 Input mode 0 1 Input mode pull up 1 0 Open drain output mode 1 1 Push pull output mode 1 0 P5 0 SEG24 Mode Selection Bits 0 ...

Page 78: ... 2 0 0 1 1 Destination page 3 0 1 0 0 Destination page 4 3 0 Source Register Page Selection Bits 0 0 0 0 Source page 0 0 0 0 1 Source page 1 0 0 1 0 Source page 2 0 0 1 1 Source page 3 0 1 0 0 Source page 4 NOTE In the S3C8247 C8249 microcontroller the internal register file is configured as five pages Pages 0 4 The pages 0 3 are used for general purpose register file and page 4 is used for LCD da...

Page 79: ...to address C0H in register set 1 selecting the 8 byte working register slice C0H C7H 2 0 Not used for the S3C8248 C8245 C8247 C8249 RP1 Register Pointer 1 D7H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte w...

Page 80: ...e 1 LSB first mode 5 SIO Mode Selection Bit 0 Receive only mode 1 Transmit receive mode 4 Shift Clock Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter ...

Page 81: ...address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL Stack Pointer Low Byte D9H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the ...

Page 82: ...T Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not execute ...

Page 83: ... IRQ2 0 1 1 IRQ3 1 0 0 IRQ4 1 0 1 IRQ5 1 1 0 IRQ6 1 1 1 IRQ7 1 Fast Interrupt Enable Bit 2 0 Disable fast interrupt processing 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit 3 0 Disable all interrupt processing 1 Enable all interrupt processing NOTES 1 You can select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt proce...

Page 84: ... 256 1 0 0 fxx 64 1 1 0 fxx 8 x x 1 fxx 4 Timer 0 Operating Mode Selection Bits Not used for the S3C8248 C8245 C8247 C8249 3 Timer 0 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write 2 Timer 0 Counter Enable Bit 0 Disable counting operation 1 Enable counting operation 1 Timer 0 Interrupt Enable Bit 0 Disable timer 0 interrupt 1 Enable timer 0 interrupt 0 Timer 0 Interrupt Pendin...

Page 85: ... clock T1CLK falling edge 1 0 1 External clock T1CLK rising edge 1 1 1 Counter stop 4 3 Timer 1 Operating Mode Selection Bits 0 0 Interval mode 0 1 Capture mode Capture on rising edge counter running OVF can occur 1 0 Capture mode Capture on falling edge counter running OVF can occur 1 1 PWM mode OVF match interrupt can occur 2 Timer 1 Counter Enable Bit 0 No effect 1 Clear the timer 1 counter whe...

Page 86: ...ction Bits 0 0 Internal mode TAOUT mode 0 1 Capture mode capture on rising edge counter running OVF can occur 1 0 Capture mode capture on falling edge counter running OVF can occur 1 1 PWM mode OVF interrupt can occur 3 Timer A Counter Clear Bit 0 No effect 1 Clear the timer A counter when write 2 Timer A Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt 1 Time...

Page 87: ...fxx 0 1 fxx 2 1 0 fxx 4 1 1 fxx 8 5 4 Timer B Interrupt Time Selection Bits 0 0 Elapsed time for low data value 0 1 Elapsed time for high data value 1 0 Elapsed time for low and high data values 1 1 Invalid setting 3 Timer B Interrupt Enable Bit 0 Disable Interrupt 1 Enable Interrupt 2 Timer B Start Stop Bit 0 Stop timer B 1 Start timer B 1 Timer B Mode Selection Bit 0 One shot mode 1 Repeating mo...

Page 88: ...Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used for the S3C8248 C8245 C8247 C8249 4 VIN Source Bit 0 Internal source 1 External source 3 VLD Output Bit 0 VIN VREF when VLD is enabled 1 VIN VREF when VLD is enabled 2 VLD Enable disable Bit 0 Disable the VLD 1 Enable the VLD 1 0 Detection Level Bits 0 0 VVLD 2 2 V 0 1 VVLD 2 4 V 1 0 VVLD 3 0 V 1 1 VVLD 4 0 V ...

Page 89: ...timer interrupt 1 Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 0 0 0 5 kHz buzzer BUZ signal output 0 1 1 kHz buzzer BUZ signal output 1 0 2 kHz buzzer BUZ signal output 1 1 4 kHz buzzer BUZ signal output 3 2 Watch Timer Speed Selection Bits 0 0 0 5 s Interval 0 1 0 25 s Interval 1 0 0 125 s Interval 1 1 1 955 ms Interval 1 Watch Timer Enable Bit 0 Disable watch timer Clear freque...

Page 90: ...e levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more int...

Page 91: ...er of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V1 one source S1 Type 2 One level IRQn one vector V1 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources S1 Sn Sn 1 Sn m In the S3C8248 C8245 C8247 C8249 microcontroller two interrupt types are implemented Vectors Sources Levels S1 V1 S2 Type 2 IRQn S3 Sn V1 S...

Page 92: ...k The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed Vectors Sources Levels Reset Clear NOTES 1 Within a given interrupt level the low vector address has high priority For example E0H has higher priority than E2H within the level IRQ 0 the priorities within e...

Page 93: ...4 Kbyte see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H 32 767 0 Decimal 255 00H 100H FFH 7FFFH HEX RESET Address Interrupt Vector Address Area 3FFFH 16 383 Internal Program Memory ...

Page 94: ...rrupt IRQ6 3 244 F4H P0 2 external interrupt 2 242 F2H P0 1 external interrupt 1 240 F0H P0 0 external interrupt 0 254 FEH P0 7 external interrupt IRQ7 3 252 FCH P0 6 external interrupt 2 250 FAH P0 5 external interrupt 1 248 F8H P0 4 external interrupt 0 NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more interrup...

Page 95: ...lags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register ID R W Function Description Interrupt mask register IMR R W Bit settings in the IMR registe...

Page 96: ... enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information Interrupt Request Register Read only IRQ0 IRQ7 Interrupts Interru...

Page 97: ...H bank 1 F3H F4H bank 1 F5H bank 1 Timer 1 overflow Timer 1 match capture IRQ3 T1CON T1CNTH T1CNTL T1DATAH T1DATAL FBH bank 1 FCH bank 1 FDH bank 1 FEH bank 1 FFH bank 1 SIO interrupt IRQ4 SIOCON SIODATA SIOPS F0H bank 0 F1H bank 0 F2H bank 0 Watch timer overflow IRQ5 WTCON FAH bank 1 P0 3 external interrupt P0 2 external interrupt P0 1 external interrupt P0 0 external interrupt IRQ6 P0CONL P0INT ...

Page 98: ...e Interrupt EI instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the EI and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Global interrupt enable bit 0 Disable all interrupts proce...

Page 99: ... level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB IRQ1 IRQ2 IRQ4 I...

Page 100: ...Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQ0 IRQ1 Group B IRQ2 IRQ3 IRQ3 Group C IRQ5 IRQ6 IRQ7 IPR Group B IPR Group C IRQ2 B1 IRQ4 B2 IRQ3 B22 B21 IRQ5 C1 IRQ7 C2 IRQ6 C22 C21 IPR Group A IRQ1 A2 IRQ0 A1 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 co...

Page 101: ... 0 IRQ0 IRQ1 1 IRQ1 IRQ0 Subgroup B 0 IRQ3 IRQ4 1 IRQ4 IRQ3 Group C 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 Subgroup C 0 IRQ6 IRQ7 1 IRQ7 IRQ6 Group B 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 Group priority 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Undefined B C A A B C B A C C A B C B A A C B Undefined D7 D4 D1 Figure 5 8 Interrupt Priority Register IPR ...

Page 102: ...gister at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it Yo...

Page 103: ...waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C8248 C8245 C8247 C8249 interrupt structure the timer 0 overflow interrupt IRQ0 belongs to this category of interrupts in which pending conditi...

Page 104: ... enabled EI SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an i...

Page 105: ...ter IMR value to the stack PUSH IMR 2 Load the IMR register with a new mask value that enables only the higher priority interrupt 3 Execute an EI instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP I...

Page 106: ...C are swapped 2 The FLAG register values are written to the FLAGS FLAGS prime register 3 The fast interrupt status bit in the FLAGS register is set 4 The interrupt is serviced 5 Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back 6 The content of FLAGS FLAGS prime is copied automatically back to the ...

Page 107: ...INTERRUPT STRUCTURE S3C8248 C8245 P8245 C8247 C8249 P8249 5 18 NOTES ...

Page 108: ...ssing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of ...

Page 109: ... LDEI dst src Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack d...

Page 110: ...rc Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ...

Page 111: ... CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR ...

Page 112: ...dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointer 1...

Page 113: ...ter can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then s...

Page 114: ... logic operations D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 ...

Page 115: ...zero 1 Set to logic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decima...

Page 116: ... addr 0 254 even number only Ir Indirect working register only Rn n 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode ...

Page 117: ... TCM r1 r2 TCM r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM BAND r0 Rb I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM BIT r1 b B 8 DECW RR1 DECW IR1 PUSHUD IR1 R2 PUSHUI IR1 R2 MULT R2 RR1 MULT IR2 RR1 MULT IM RR1 LD r1 x r2 B 9 RL R1 RL IR1 POPUD IR2 R1 POPUI IR2 R1 DIV R2 RR1 DIV IR2 RR1 DIV IM RR1 LD r2 x r1 L A INCW RR1 INCW IR1 CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM LDC ...

Page 118: ...ed OPCODE MAP LOWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NEXT P 1 ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NOP ...

Page 119: ... Z Zero Z 1 1110 note NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 note EQ Equal Z 1 1110 note NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 note UGE Unsigned greater than or equal C 0 0111 note ULT Unsigned less than C 1...

Page 120: ...fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time...

Page 121: ...curs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R...

Page 122: ...are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R2 03H ADD R...

Page 123: ...cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Register ...

Page 124: ... Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 67 r0 Rb opc src b 1 dst 3 6 67 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 R1 06H register 01H 05H BAND 01H 1 R1 Re...

Page 125: ...Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 17 r0 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H and register 01H 01H BCP R1 01H 1 R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the s...

Page 126: ...ffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 57 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination an...

Page 127: ... are affected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R1 1 R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination regi...

Page 128: ...ffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 R1 0FH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination registe...

Page 129: ...econd byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Examples Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03...

Page 130: ...ags are affected Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJ...

Page 131: ... are affected Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in...

Page 132: ... Addr Mode dst src opc dst b 0 src 3 6 27 r0 Rb opc src b 1 dst 3 6 27 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 R1 06H register 01H 03H BXOR 01H 2 R1 Register 01H 07H R1 07H ...

Page 133: ...t follows the instruction CALL RR0 SP 0000H 0000H 1AH 0001H 49H CALL 40H SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value 3521H the address of t...

Page 134: ... of the carry flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ...

Page 135: ...r Mode dst opc dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ...

Page 136: ... H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value 0F8H 11111000...

Page 137: ... A3 r lr opc src dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S ar...

Page 138: ...are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The...

Page 139: ...at Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 04H CPIJNE R1 R2 SKIP R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The sta...

Page 140: ...tion Carry Before DA Bits 4 7 Value Hex H Flag Before DA Bits 0 3 Value Hex Number Added to Byte Carry After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 F 0 0 9 A0 60 1 1 6 F 1 6 F 9A 66 1 Flags C Set if there was a carry from t...

Page 141: ... values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0 0 0 1 0 1 0 1 15 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 42 Assuming the same values gi...

Page 142: ...flow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R...

Page 143: ...at Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples Given R0 12H R1 34H R2 30H register 30H 0FH and register 31H 21H DECW RR0 R0 12H R1 33H DECW R2 Register 30H 0FH register 31H 20H In the first example destination register R0 contains the value 12H and register R1 the value 34H The statement DECW RR0 addresses R0 and the following operand R1 as a 16 bit word and decrements...

Page 144: ...t their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending a...

Page 145: ...f MSB of quotient 1 cleared otherwise V Set if quotient is 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given R0 10H R1 03H R2 40H register 40H 80H DIV RR0 R2 R0 03H R1 40...

Page 146: ...ng register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP SRP0 or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst r opc dst 2 8 jump taken rA RA 8 no jump r 0 to F Example Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases...

Page 147: ... interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all...

Page 148: ... pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement 0050 IP 0022 SP 22 Data Address Data 0040 PC 40 41 42 43 Enter Address H Address L Address H Address Data 1F 01 10 Memory 0043 IP 0020 SP 20 ...

Page 149: ...uction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement 0050 IP 0022 SP Address Data 0040 PC Address Data Memory 0052 IP 0022 SP Address Data 0060 PC Address Data Memory S...

Page 150: ...tops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but not the system clock ...

Page 151: ...e Hex Addr Mode dst dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 4 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INC R0 R0 1CH INC 00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The next example shows the effect an INC instruction has...

Page 152: ... 1AH R1 02H register 02H 0FH and register 03H 0FFH INCW RR0 R0 1AH R1 03H INCW R1 Register 02H 10H register 03H 00H In the first example the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1 The statement INCW RR0 increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register IR a...

Page 153: ...al stack IRET Fast Bytes Cycles Opcode Hex opc 1 6 BF Example In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally...

Page 154: ... NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL_W 1000H PC 1000H JP 00H PC 0120H The first example shows a conditional JP Assu...

Page 155: ...7 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format 1 Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Example Given The carry flag 1 and LABEL_X 1FF...

Page 156: ...he source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r 0 to F opc dst src 2 4 C7 r lr 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r opc src dst x 3 6 97 x r r ...

Page 157: ... R0 20H register 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1 Register 31...

Page 158: ...ruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R0 06H and general register 00H 05H LDB R0 00H 2 R0 07H register 00H 05H LDB 00H 0 R0 R0 06H register 00H 04H In the first example destination working register R0 contains the value 06H and the source general register 00H the value 05H The sta...

Page 159: ...st src XS 3 12 E7 r XS rr 4 opc src dst XS 3 12 F7 XS rr r 5 opc dst src XLL XLH 4 14 A7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 opc dst 0000 DAL DAH 4 14 A7 r DA 8 opc src 0000 DAL DAH 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and ...

Page 160: ...am memory location 0105H 01H RR2 R0 6DH R2 01H R3 04H LDE R0 01H RR2 R0 contents of external data memory location 0105H 01H RR2 R0 7DH R2 01H R3 04H LDC note 01H RR2 R0 11H contents of R0 is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 R0 11H contents of R0 is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 R0 contents of program memory location 1104H ...

Page 161: ...ce are unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0DDH...

Page 162: ...source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 1033H 0DDH and ...

Page 163: ...estination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F2 Irr r Examples Given R0 77H R6 30H and R7 00H LDCPD RR6 R0 RR6 RR6 1...

Page 164: ... destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F3 Irr r Examples Given R0 7FH R6 21H and R7 0FFH LDCPI RR6 R0 RR6 RR6 1 7FH c...

Page 165: ...egister 02H 03H and register 03H 0FH LDW RR6 RR4 R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H Register 00H 03H register 01H 0FH register 02H 03H register 03H 0FH LDW RR2 R7 R2 03H R3 0FH LDW 04H 01H Register 04H 03H register 05H 0FH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H 0FH register 03H 0EDH In the second example please note that the statement LDW 00H 02H loads the contents of the sour...

Page 166: ...if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H Register 00H 00H register 01H 0C0H MULT 00H 30H Register 00H...

Page 167: ... into the program counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 0F Example The following diagram shows one example of how to use the NEXT instruction Data 01 10 Before After 0045 IP Address Data 0130 PC 43 44 45 Address H Address L Address H Address Data Memory 130 Routine 0043 IP Address Data 0120 PC 43 44 45 Address...

Page 168: ...tes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ...

Page 169: ...H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H register 01H 0BFH OR ...

Page 170: ...ddr Mode dst opc dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H 0FBH and stack register 0FBH 55H POP 00H Register 00H 55H SP 00FCH POP 00H Register 00H 01H register 01H 55H SP 00FCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 00FBH 55H into destination register 00H and then increm...

Page 171: ...nter is then decremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 92 R IR Example Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H Register 00H 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads ...

Page 172: ... user stack pointer is then incremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 00H Register 00H 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destina...

Page 173: ... opc src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SPH 00H and SPL 00H PUSH 40H Register 40H 4FH stack register 0FFH 4FH SPH 0FFH SPL 0FFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0FFH 0AAH SPH 0FFH SPL 0FFH In the first example if the stack pointer contains the value 0000H and general regist...

Page 174: ...emented stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 82 IR R Example Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by on...

Page 175: ...remented user stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 83 IR R Example Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer...

Page 176: ...ry Flag RCF RCF Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ...

Page 177: ...ent that is executed is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Example Given SP 00FCH SP 101AH and PC 1234 RET PC 101AH SP 00FEH The statement RET pops the contents of stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the va...

Page 178: ...the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the first exampl...

Page 179: ... Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if general regi...

Page 180: ...ic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 E0 R 4 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the v...

Page 181: ...Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 C0 R 4 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if general regist...

Page 182: ...truction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SB0 clears FLAGS 0 to 0 selecting bank 0 register addressing ...

Page 183: ...in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented ...

Page 184: ...ow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6...

Page 185: ... 78 SCF Set Carry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to logic one ...

Page 186: ... otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 D0 R 4 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if general register 00H contains the value 9AH 10...

Page 187: ...ine whether to write one or both of the register pointers RP0 and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode src opc src 2 4 31 IM Examples The statement SRP 40H sets register pointer 0 RP0 at location 0D6H ...

Page 188: ... CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 7F Example Th...

Page 189: ...d cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH SUB R1 R...

Page 190: ...he result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 F0 R 4 F1 IR Examples Given Register 00H 3EH register 02H 03H and register 03H 0A4H SWAP 00H Register 00H 0E3H SWAP 02H Register 02H 03H register 03H 4AH In the first example if general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the...

Page 191: ... V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH register 01H 02H...

Page 192: ...d H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 00H 2BH regi...

Page 193: ...atus can be released by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI statement EI WFI Next instruction Main program Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed Enable g...

Page 194: ...set to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 B2 r r 6 B3 r lr opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H 01H Register ...

Page 195: ...INSTRUCTION SET S3C8248 C8245 P8245 C8247 C8249 P8249 6 88 NOTES ...

Page 196: ...CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON XIN XOUT C1 C2 S3C8248 C8245 C8247...

Page 197: ... operating with sub system clock In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt 1 8 1 4096 Frequency Dividing Circuit Stop Release Main System Oscillator Circuit Selector 1 fX fXT Stop Driving Ability Sub system Oscillator Circuit OSCCON 4 INT OSCCON 0 OSCCO...

Page 198: ...clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Not used must keep always 0 Not used must keep always 0 Divide by selection bits for CPU clock frequency 00 fXX 16 01 fXX 8 10 fXX 2 11 fXX 1 non divided NOTE The fxx can be generated by both main system and ...

Page 199: ...y NOTE In strong mode the warm up time is less than 100 ms When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer counter clock input Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms 100 ms Here the warm up time is from the time that the stop relea...

Page 200: ...their default hardware values In summary the following sequence of events occurs during a reset operation All interrupt is disabled The watchdog function basic timer is enabled Ports 0 3 and set to input mode Peripheral control and data register settings are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the...

Page 201: ...ex 7 6 5 4 3 2 1 0 LCD Control Register LCON 208 D0H 0 0 0 0 0 0 0 0 LCD Mode Register LMOD 209 D1H 0 0 0 0 0 0 0 0 Interrupt Pending Register INTPND 210 D2H 0 0 0 0 0 0 0 0 Basic Timer Control Register BTCON 211 D3H 0 0 0 0 0 0 0 0 Clock Control Register CLKCON 212 D4H 0 0 0 0 0 0 0 0 System Flags Register FLAGS 213 D5H x x x x x x 0 0 Register Pointer High Byte RP0 214 D6H 1 1 0 0 0 Register Poi...

Page 202: ...B Data Register Low Byte TBDATAL 235 EBH 1 1 1 1 1 1 1 1 Timer B Control Register TBCON 236 ECH 0 0 0 0 0 0 0 0 Timer A Control Register TACON 237 EDH 0 0 0 0 0 0 0 0 Timer A Counter Register TACNT 238 EEH 0 0 0 0 0 0 0 0 Timer A Data Register TADATA 239 EFH 1 1 1 1 1 1 1 1 Serial I O Control Register SIOCON 240 F0H 0 0 0 0 0 0 0 0 Serial I O Data Register SIODATA 241 F1H 0 0 0 0 0 0 0 0 Serial I ...

Page 203: ...ounter Register Low Byte T0CNTL 243 F3H 0 0 0 0 0 0 0 0 Timer 0 Data Register High Byte T0DATAH 244 F4H 1 1 1 1 1 1 1 1 Timer 0 Data Register Low Byte T0DATAL 245 F5H 1 1 1 1 1 1 1 1 Voltage Level Detector Control Register VLDCON 246 F6H 0 0 0 0 0 0 0 0 AD Converter Control Register ADCON 247 F7H 0 0 0 0 0 0 0 0 AD Converter Data Register High Byte ADDATAH 248 F8H x x x x x x x x AD Converter Data...

Page 204: ... an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C8248 C8245 C8247 C8249 interrupt structure that can be used to release Stop mode are External interrupts P0 0 P0 7 INT0 INT7 Please note the following conditions fo...

Page 205: ...m and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idl...

Page 206: ... trigger input or output mode selected by software software assignable pull up P0 0 P0 7 can be used as inputs for external interrupts INT0 INT7 with noise filter and interrupt control 1 1 bit programmable I O port Input or output mode selected by software open drain output mode can be selected by software software assignable pull up Alternately P1 0 P1 7 can be used as SI SO SCK BUZ T1CAP T1CLK T...

Page 207: ...and 5 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary Register Name Mnemonic Decimal Hex Location R W Port 0 data register P0 246 F6H Set 1 Bank 0 R W Port 1 data register P1 247 F7H Set 1 Bank 0 R W Port 2 data register P2 248 F8H Set 1 Bank 0 R W Port 3 data register P3 249 F9H Set 1 Bank 0 R W Port 4 data register P4 250 FAH Set 1 Bank 0 R W Port 5 data register...

Page 208: ...ing rising signal edges Port 0 Interrupt Enable and Pending Registers P0INT P0PND To process external interrupts at the port 0 pins two additional control registers are provided the port 0 interrupt enable register P0INT E2H set 1 bank 0 and the port 0 interrupt pending register P0PND E3H set 1 bank 0 The port 0 interrupt pending register P0PND lets you check for interrupt pending conditions and c...

Page 209: ...rigger input mode interrupt on rising or falling edge Output mode push pull Figure 9 1 Port 0 High Byte Control Register P0CONH Port 0 Control Register Low Byte P0CONL E1H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P0 3 INT3 P0 2 INT2 P0 1 INT1 P0 0 INT0 P0CONL bit pair pin configuration 00 01 10 11 Schmitt trigger input mode pull up interrupt on falling edge Schmitt trigger input mode interrupt on ...

Page 210: ...INT5 INT4 INT3 INT2 INT1 INT0 Interrupt Enable Figure 9 3 Port 0 Interrupt Control Register P0INT Port 0 Interrupt Pending Register P0PND E3H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P0PND bit configuration settings 0 1 PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0 Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending Figure 9 4 Port 0 Interrupt Pending Register P0...

Page 211: ...select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Pull up Resistor Enable Register P1PUP Using the port 1 pull up resistor enable register P1PUP F5H set 1 bank 0...

Page 212: ...ode Output mode push pull P1 2 T1OUT T1PWM P1 1 T1CLK P1 0 T1CAP Output mode open drain NOTE When use this port 1 user must be care of the pull up resistance status Input mode T1CAP T1CLK Figure 9 6 Port 1 Low Byte Control Register P1CONL Port 1 Pull up Control Register F5H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P1PUP bit configuration settings 0 1 Pull up Disable P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P...

Page 213: ...k 0 for pins P2 0 P2 3 and P2CONH E6H set 1 Bank 0 for pins P2 4 P2 7 Each byte contains four bit pairs and each bit pair configures one port 2 pin The P2CONH and the P2CONL registers also control the alternative functions Port 2 Control Register High Byte P2CONH E6H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P2 7 VLDREF ADC7 P2 6 ADC6 P2 5 ADC5 P2 4 ADC4 P2CONH bit pair pin configuration 00 01 10 1...

Page 214: ... bit pair pin configuration 00 01 10 11 Alternative function ADC mode Output mode push pull Input mode pull up NOTE If a pin is enabled for ADC mode by ADCEN normal I O and pull up resistance are disabled When pins are enabled for ADC mode by ADCEN the pins can be selected for ADC input by ADCON 6 5 4 P2 3 ADC3 Input mode Figure 9 9 Port 2 Low Byte Control Register P2CONL ...

Page 215: ... 4 and P3CONL for P3 0 P3 3 A reset clears the P3CONH and P3CONL registers to 00H configuring all pins to input mode You use control registers settings to select input or output mode enable pull up resistors and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabl...

Page 216: ...5 4 3 2 1 0 MSB LSB P3 2 TACLK P3 1 TAOUT TAPWM P3 0 TBPWM P3CONL bit pair pin configuration settings 00 01 10 11 Alternative function TAOUT TAPWM TBPWM P3 2 P3 3 is push pull output mode Output mode push pull Input mode pull up TACAP P3 3 TACAP Input mode TACAP TACLK Figure 9 11 Port 3 Control Low Register P3CONL ...

Page 217: ... Control Registers Port 4 has two 8 bit control registers P4CONH for P4 4 P4 7 and P4CONL for P4 0 P4 3 A reset clears the P4CONH and P4CONL registers to 00H configuring all pins to input mode Output mode push pull Port 4 Control Register High Byte ECH Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB P4 6 SEG22 P4 5 SEG21 P4 4 SEG20 P4CONH bit pair pin configuration settings 00 01 10 11 Input mode pull up...

Page 218: ...0 MSB LSB P4 2 SEG18 P4 1 SEG17 P4 0 SEG16 P4CONL bit pair pin configuration settings 00 01 10 11 Output mode push pull Input mode pull up P4 3 SEG19 Input mode Opendrain output mode NOTE If LCD is enabled by LCON 4 SEG signal go out otherwise port 4 I 0 can be selected Figure 9 13 Port 4 Low Byte Control Register P4CONL ...

Page 219: ...ontrol Registers Port 5 has two 8 bit control registers P5CONH for P5 4 P5 7 and P5CONL for P5 0 P5 3 A reset clears the P5CONH and P5CONL registers to 00H configuring all pins to input mode Output mode push pull Port 5 Control Register High Byte EEH Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB P5 6 SEG30 P5 5 SEG29 P5 4 SEG28 P5CONH bit pair pin configuration settings 00 01 10 11 Input mode pull up P...

Page 220: ...k 1 R W 7 6 5 4 3 2 1 0 MSB LSB P5 2 SEG26 P5 1 SEG25 P5 0 SEG24 P5CONL bit pair pin configuration settings 00 01 10 11 Input mode pull up P5 3 SEG27 Input mode Opendrain output mode NOTE If LCD is enabled by LCON 6 SEG signal go out otherwise port 5 I 0 can be selected Figure 9 15 Port 5 Low Byte Control Register P5CONL ...

Page 221: ...I O PORTS S3C8248 C8245 P8245 C8247 C8249 P8249 9 16 NOTES ...

Page 222: ...mer control register BTCON set 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A reset clears BTCON to 00H T...

Page 223: ... Divider clear bit 0 No effect 1 Clear dvider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fXX 4096 01 fXX 1024 10 fXX 128 11 fXX 16 Watchdog timer enable bits 1010B Disable watchdog function Other value Enable watchdog function Figure 10 1 Basic Timer Control Register BTCON ...

Page 224: ...broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an external interrupt occurs the oscillator starts Th...

Page 225: ...cillation stabilization interval until bit 4 of the basic timer counter overflows MUX fXX 4096 DIV fXX 1024 fXX 128 fXX 16 fXX Bits 3 2 Bit 0 Basic Timer Control Register Write 1010xxxxB to Disable Clear Bit 1 RESET or STOP Data Bus 8 Bit Up Counter BTCNT Read Only Start the CPU NOTE OVF RESET R Figure 10 2 Basic Timer Block Diagram ...

Page 226: ...ode with a rising or falling edge trigger at the TACAP pin PWM mode TAPWM Timer A has the following functional components Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer External clock input pin TACLK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register TADATA I O pins for capture input TACAP or PWM or match output TAPWM TAOUT Timer A overflow interrupt IRQ...

Page 227: ...e TAPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H Although timer A overflow interrupt is occurred this interrupt is not typically used in PWM typ...

Page 228: ...e vector address E2H When a timer A overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware Timer A Control Register EDH Set 1 Bank 0 R W RESET 00H 7 6 5 4 3 2 1 0 MSB LSB Timer A match capture interrupt enable bit 0 DIsable interrupt 1 Enable interrupt Timer A match capture interrupt pending bit 0 No interrupt pending 0 Clear pending bit wri...

Page 229: ... Read Only Clear Match TACON 7 6 fXX 1024 fXX 256 fXX 64 TACLK TACON 2 Pending TACON 3 M U X Overflow TAOVF M U X M U X TACAP TAINT TACON 1 TAOUT TAPWM TACON 0 Pending TACON 5 4 TACON 5 4 Data Bus 8 Data Bus 8 NOTE Timer A input clock must be slower than CPU clock Pending Pending bit is located at INTPND register Figure 11 2 Timer A Functional Block Diagram ...

Page 230: ...ting the timer 0 overflow interrupt 8 bit Down Counter Timer B Data High Byte Register MUX TBCON 0 TBOF To Other Block P3 0 TBPWM IRQ1 TBINT INT GEN TBCON 3 Repeat Control Interrupt Control M U X fXX 1 fXX 2 fXX 4 fXX 8 TBCON 6 7 TBCON 2 Timer B Data Low Byte Register CLK TBCON 4 5 Data Bus 8 NOTES 1 The value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer...

Page 231: ...le interrupt 1 Enable interrupt Timer B input clock selection bits 00 fxx 01 fxx 2 10 fxx 4 11 fxx 8 Timer B interrupt time selection bits 00 Elapsed time for low data value 01 Elapsed time for high data value 10 Elapsed time for low and high data values 11 Invalid setting Figure 11 4 Timer B Control Register TBCON Timer B Data High Byte Register TBDATAH FAH Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LS...

Page 232: ...DATAH 2 x 1 fx 0H TBDATAH 100H where fx The selected clock When TBOF 1 tLOW TBDATAH 2 x 1 fx 0H TBDATAH 100H where fx The selected clock tHIGH TBDATAL 2 x 1 fx 0H TBDATAL 100H where fx The selected clock To make tLOW 24 us and tHIGH 15 us fOSC 4 MHz fx 4 MHz 4 1 MHz When TBOF 0 tLOW 24 us TBDATAL 2 fx TBDATAL 2 x 1us TBDATAL 22 tHIGH 15 us TBDATAH 2 fx TBDATAH 2 x 1us TBDATAH 13 When TBOF 1 tHIGH ...

Page 233: ...TAH 01 FFH TBOF 0 TBDATAL 00H TBDATAH 00H TBOF 1 TBDATAL 00H TBDATAH 00H Low High Low High Timer B Clock TBOF 1 TBDATAL DEH TBDATAH 1EH TBOF 0 TBDATAL DEH TBDATAH 1EH TBOF 1 TBDATAL 7EH TBDATAH 7EH TBOF 0 TBDATAL 7EH TBDATAH 7EH 0H 100H 200H E0H 20H 20H E0H 80H 80H 80H 80H Figure 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode ...

Page 234: ...s 37 9 kHz 1 3 Duty 8 795 µs Timer B is used in repeat mode Oscillation frequency is 4 MHz 0 25 µs TBDATAH 8 795 µs 0 25 µs 35 18 TBDATAL 17 59 µs 0 25 µs 70 36 Set P3 0 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAL 70 2 Set 17 5 µs LD TBDATAH 35 2 Set 8 75 µs LD TBCON 00000110B Clock Source fxx Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer ...

Page 235: ...ncy is 4 MHz 1 clock 0 25 µs TBDATAH 40 µs 0 25 µs 160 TBDATAL 1 Set P3 0 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAH 160 2 Set 40 µs LD TBDATAL 1 Set any value except 00H LD TBCON 00000001B Clock Source fOSC Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop TBOF high LD P3CONL 02H Set P3 0 to TBPWM mode Pulse_out LD TBCON ...

Page 236: ...NT belongs to interrupt level IRQ2 and is assigned the separate vector address E6H The T0INT pending condition is automatically cleared by hardware when it has been serviced Even though T0INT is disabled the application s service routine can detect a pending condition of T0INT by the software and execute it s sub routine When this case is used the T0INT pending bit must be cleared by the applicati...

Page 237: ...ite T0CON 3 and 0 which cleared counter and interrupt pending bit To detect an interrupt pending condition when T0INT is disabled the application program polls pending bit T0CON 0 When a 1 is detected a timer 0 interrupt is pending When the T0INT sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the timer 0 interrupt pending bit T0CON 0 Timer 0 Contr...

Page 238: ... H L Read Only Match Bit 3 T0INT Counter clear signal T0CON 3 Bits 7 6 5 M U X fxx 256 fxx 64 fxx 8 fxx 1 TBOF Bit 2 Clear Bit 0 Bit 1 IRQ2 Pending R Data Bus 8 Data Bus 8 NOTES 1 To be loaded T0DATA value to buffer register for comparing T0CON 3 bit must be set 1 2 Timer 0 input clock must be slower than CPU clock Figure 12 2 Timer 0 Functional Block Diagram ...

Page 239: ...ter Low Byte T0CNTL F3H Set 1 Bank 1 R 7 6 5 4 3 2 1 0 MSB LSB Reset Value 00H Figure 12 3 Timer 0 Counter Register T0CNT Timer 0 Data High Byte Register T0DATAH F4H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFh Timer 0 Data Low Byte Register T0DATAL F5H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFh Figure 12 4 Timer 0 Data Register T0DATAH L ...

Page 240: ...or falling edge trigger at the T1CAP pin PWM mode T1PWM Timer 1 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 or 1 with multiplexer External clock input pin T1CLK 16 bit counter T1CNTH L 16 bit comparator and 16 bit reference data register T1DATAH L I O pins for capture input T1CAP or PWM or match output T1PWM T1OUT Timer 1 overflow interrupt IRQ3 vec...

Page 241: ...al is generated when the counter value is identical to the value written to the timer 1 data register In PWM mode however the match signal does not clear the counter but can generate a match interrupt The counter runs continuously overflowing at FFFFH and then repeat the incrementing from 0000H Whenever an overflow is occurred an overflow OVF interrupt can be generated Although you can use the mat...

Page 242: ...CON by the CPU the pending condition is cleared automatically by hardware To enable the timer 1 match capture which clear counter and interrupt pending bit To detect a match capture or overflow interrupt pending condition when T1INT or T1OVF is disabled the application program should poll the pending bit When a 1 is detected a timer 1 match capture or overflow interrupt is pending When her sub rou...

Page 243: ...56 fXX 64 fXX 1 T1OVF IRQ3 T1CON 0 OVF Pending T1CON 2 T1INT IRQ3 Pending T1CON 1 T1OUT T1PWM T1CON 4 3 R M U X VSS T1CLK M U X M U X T1CAP T1CON 4 3 Data Bus 8 Data Bus 8 Pending Pending bit is located at INTPND register NOTES 1 16 bit PWM frequency Where 10 MHz clock is used and fxx 8 is selected PWM frequency 1 8 10 MHz x FFFFh 19 07 Hz 2 Timer 1 input clock must be slower than CPU clock Figure...

Page 244: ...LSB Timer 1 Counter Low Byte Register T1CNTL FDH Set 1 Bank 1 R Reset Value 00H 7 6 5 4 3 2 1 0 LSB Timer 1 Data High Byte Register T1DATAH FEH Set 1 Bank 1 R W Reset Value FFh MSB 7 6 5 4 3 2 1 0 LSB Timer 1 Data Low Byte Register T1DATAL FFH Set 1 Bank 1 R W Reset Value FFh MSB NOTE Pending bit is located in INTPND D2H set1 register Figure 12 7 Timer 1 Control Register T1CNTH L ...

Page 245: ...16 BIT TIMER 0 1 S3C8248 C8245 P8245 C8247 C8249 P8249 12 10 NOTES ...

Page 246: ...second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 1 955 ms High speed mode is useful for timing events for program debugging sequences The watch timer supplies the clock frequency for the LCD controller fLCD Therefore if ...

Page 247: ...h timer interrupt 1 Enable watch timer interrupt WTCON 5 4 0 0 0 5 kHz buzzer BUZ signal output 0 1 1 kHz buzzer BUZ signal output 1 0 2 kHz buzzer BUZ signal output 1 1 4 kHz buzzer BUZ signal output WTCON 3 2 0 0 Set watch timer interrupt to 0 5 s 0 1 Set watch timer interrupt to 0 25 s 1 0 Set watch timer interrupt to 0 125 s 1 1 Set watch timer interrupt to 1 955 ms WTCON 1 0 Disable watch tim...

Page 248: ...t MUX WTCON 0 WTINT WTCON 6 BUZZER Output fW 214 fW 213 fW 212 fW 26 fW 64 0 5 kHz fW 32 1 kHz fW 16 2 kHz fW 8 4 kHz 1 Hz fxx Main System Clock 4 19 MHz fXT Subsystem Clock 32768 Hz fw Watch timer Clock Selector WTCON 7 Frequency Dividing Circuit fW 32 768 kHz fXT fxx 128 fLCD 512 HZ fVLD 4096 HZ fBOOSTER 4096 HZ Figure 13 1 Watch Timer Circuit Diagram ...

Page 249: ...WATCH TIMER S3C8248 C8245 P8245 C8247 C8249 P8249 13 4 NOTES ...

Page 250: ...er LCD bias by voltage dividing resistors Bit settings in the LCD mode register LMOD determine the LCD frame frequency duty and bias and the segment pins used for display output When a subsystem clock is selected as the LCD clock source the LCD display is enabled even during stop and idle modes The LCD control register LCON turns the LCD display on and off and switches current to the charge pump c...

Page 251: ...troller 05H 1 05H 0 04H 7 04H 6 00H 3 00H 2 00H 1 00H 0 OFH 4 OFH 5 OFH 6 OFH 7 MUX MUX MUX 8 8 8 8 8 fLCD COM Control COM1 VLC0 VLC1 VLC2 CA CB SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG0 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 Segment Driver NOTE fLCD fW 26 fW 27 fW 28 fW 29 LCD Voltage Control Figure 14 2 LCD Circuit Diagram ...

Page 252: ... for LCD display can be allocated to general purpose use SEG0 BIT 7 BIT 3 BIT 7 BIT 3 BIT 7 BIT 3 BIT 7 BIT 3 BIT 7 BIT 3 BIT 3 BIT 7 BIT 3 BIT 7 BIT 3 BIT 7 BIT 3 BIT 7 BIT 6 BIT 2 BIT 6 BIT 2 BIT 6 BIT 2 BIT 6 BIT 2 BIT 6 BIT 2 BIT 2 BIT 6 BIT 2 BIT 6 BIT 2 BIT 6 BIT 2 BIT 6 BIT 5 BIT 1 BIT 5 BIT 1 BIT 5 BIT 1 BIT 5 BIT 1 BIT 5 BIT 1 BIT 1 BIT 5 BIT 1 BIT 5 BIT 1 BIT 5 BIT 1 BIT 5 BIT 4 BIT 0 BI...

Page 253: ...ways logic zero LCON 2 0 Enable LCD initial circuit internal bias voltage 1 Disable LCD initial circuit for external LCD dividing resistors external bias voltage LCON 1 0 Stop voltage booster clock stop and cut off current charge path 1 Run voltage booster clock run and turn on current charge path LCON 0 0 LCD output low turn display off COM and SEG output Low Cut off voltage booster Booster clock...

Page 254: ...timer must be enabled when the LCD display is turned on RESET clears the LMOD register values to logic zero This produces the following LCD control settings Display is turned off LCDCK frequency is the watch timer clock fw 29 64 Hz The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source The LCD output voltage level is always 3 V sup...

Page 255: ...256 Hz 1 1 32 768 kHz watch timer clock fw 26 512 Hz LMOD 3 LMOD 2 LMOD 1 LMOD 0 Duty and Bias Selection for LCD Display 0 x x x LCD display off COM and SEG output Low 1 0 0 0 1 4 duty 1 3 bias 1 0 0 1 1 3 duty 1 3 bias 1 0 1 1 1 3 duty 1 2 bias 1 0 1 0 1 2 duty 1 2 bias 1 1 x x Static NOTE x means don t care Table 14 5 Maximum Number of Display Digits per Duty Cycle LCD Duty LCD Bias COM Output P...

Page 256: ... VLC0 1 2 VLCD 1 3 VLCD Vss 0 V 0 V 0 V NOTE The LCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment signal voltage Therefore always drive the LCD panel with AC voltage LCD SEG SEG SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at 00H 0FH Bits 0 3 and 4 7 of the display RAM are synchronized with the comm...

Page 257: ... 2 VLC 0 Vss SEG Vss COM SEG Vss VLC 0 VLC1 2 VLC1 2 VLC 0 VLC1 2 VLC 0 Figure 14 5 Select No Select Bias Signals in 1 2 Duty 1 2 Bias Display Mode FR Select Non Select 1 Frame SEG COM COM SEG VLC 2 VSS VLC 2 VSS VLC 2 VSS VLC 2 Figure 14 6 Select No Select Bias Signals in 1 3 Duty 1 3 Bias Display Mode ...

Page 258: ...ta Register page 4 address 00H LD 00H 31h Data Register page 4 address 01H LD 01H 12h COM0 COM1 SEG2 1 x C1 SEG0 0 x C0 SEG0 1 x C1 SEG1 0 x C0 SEG3 0 x C0 SEG2 1 x C1 SEG2 0 x C0 SEG2 0 x C0 SEG1 1 x C1 VLC1 2 VSS VLC0 VLC1 2 VSS VLC0 VLC1 2 VSS VLC0 VLC1 2 VSS VLC0 VLC1 2 VLC1 2 VLC0 VSS VLC0 VLC1 2 VLC1 2 VLC0 VSS VLC0 VLC1 2 VLC1 2 VLC0 VSS VLC0 VLC1 2 VLC1 2 VLC0 VSS VLC0 Figure 14 7 LCD Sign...

Page 259: ...x C2 SEG2 0 x C0 SEG1 5 x C1 SEG0 1 x C1 COM0 COM1 SEG0 Data Register page 4 address 00H LD 00H 16h SEG1 1 0 0 X 4 5 6 7 SEG2 1 1 0 X 0 1 2 3 COM2 VLC2 VLC1 VLC1 VLC0 VSS VLC0 VLC2 VLC2 VLC1 VLC1 VLC0 VSS VLC0 VLC2 VLC2 VLC1 VLC1 VLC0 VSS VLC0 VLC2 VLC2 VLC1 VLC1 VLC0 VSS VLC0 VLC2 0 1 2 3 0 1 1 X SEG3 SEG4 1 1 0 X 0 1 2 3 Data Register page 4 address 02H LD 02H 33h SEG5 1 1 0 X 4 5 6 7 Data Regis...

Page 260: ... VSS VLC0 VLC2 VLC2 VSS VLC1 VLC0 VLC2 VSS VLC1 VLC0 SEG1 COM1 SEG0 SEG1 7 x C3 SEG2 1 x C1 SEG1 4 x C0 SEG0 0 x C0 SEG0 1 x C1 SEG1 5 x C1 SEG0 3 x C3 SEG2 0 x C0 SEG1 6 x C2 SEG0 2 x C2 COM0 COM1 COM2 Data Register page 4 address 01H LD 01H 7Ah SEG2 0 1 0 1 0 1 2 3 SEG3 1 1 1 0 4 5 6 7 Data Register page 4 address 02H LD 02H 63h SEG4 1 1 0 0 0 1 2 3 SEG5 0 1 1 0 4 5 6 7 COM3 Data Register page 4...

Page 261: ...tage Dividing Resistors Externally For make external voltage dividing resistors Make enable the watch timer Set LCON 2 to 1 and LCON 1 to 0 for make disable voltage booster Make floating the CA and CB pin Recommendable R 100 KΩ VDD VLC2 VLC1 VLC0 VSS 2 x R R R R VDD VLC2 VLC1 VLC0 VSS R R R Static and 1 3 Bias VLCD 3 V at VDD 5 V 1 2 Bias VLCD 3 3 V at VDD 5 V VDD VLC2 VLC1 VLC0 VSS R R R Static a...

Page 262: ...itch are not used for ADC can be used for normal I O During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select di...

Page 263: ...input pin selection bits 4 5 and 6 End of conversion status detection bit 3 A D operation start or enable bit 0 After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADC0 ADC7 can be selected dynamically by manipulating the ADCON 4 6 bits And the pins not used for analog input can be used for normal I O function Start or enable bit...

Page 264: ... Data Register ADDATAH L INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVSS to AVREF usually AVREF VDD Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference vol...

Page 265: ...nk 1 Upper 8 bit is loaded to A D Conversion Data Register To ADCON 3 EOC Flag Successive Approximation Logic Register AVREF AVSS Analog Comparator 10 bit D A Converter M U X ADCON 4 6 Select one input pin of the assigned pins ADCEN 0 7 Assign Pins to ADC Input ADCON 0 AD C Enable ADCON 0 AD C Enable ADCON 2 1 Figure 15 3 A D Converter Functional Block Diagram ...

Page 266: ...tor with a value of from 50 to 100Ω If this resistor is omitted the absolute accuracy will be maximum of 3 LSBs VSS S3C8248 C8245 C8247 C8249 ADC0 ADC7 AVREF Reference Voltage Input Analog Input Pin R VDD VDD 10 uF 103 C 101 C Figure 15 4 Recommended A D Converter Circuit for Highest Absolute Accuracy ...

Page 267: ...A D CONVERTER S3C8248 C8245 P8245 C8247 C8249 P8249 15 6 NOTES ...

Page 268: ...re flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO modules follow these basic steps 1 Configure the I O pins at port SO SCK SI by loading the appropriate value to the P1CONH register if necessary 2 Load an 8 bit value to the SIOCON control register to properly configure the serial I O module In this operation SIOCON 2 mu...

Page 269: ...ion and the interrupt are disabled The selected data direction is MSB first Serial I O Module Control Registers SIOCON F0H Set 1 Bank 0 R W RESET 00H 7 6 5 4 3 2 1 0 MSB LSB SIO interrupt enable bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending SIO shift operation enable bit 0 Disable shif...

Page 270: ...ock where the input clock is fxx 4 SIO Pre scaler Register SIOPS F2H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Baud rate fXX 4 SIOPS 1 Figure 16 2 SIO Pre scale Registers SIOPS BLOCK DIAGRAM SIO INT Pending 3 Bit Counter Clear SIOCON 0 fxx 2 SIOPS F2H bank 0 SCK SIOCON 7 Prescaler Value 1 SIOPS 1 SIOCON 1 Interrupt Enable CLK SI SIOCON 3 Data Bus SO M U X 1 2 8 bit P S IRQ4 8 8 Bit SIO Shift Buffer...

Page 271: ...DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI SCK Figure 16 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 IRQS DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK Transmit Complete SI SO Set SIOCON 3 Figure 16 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 ...

Page 272: ...ION The voltage booster has built for driving the LCD The voltage booster provides the capability of directly connecting an LCD panel to the MCU without having to separately generate and supply the higher voltages required by the LCD panel The voltage booster operates on an internally generated and regulated LCD system voltage and generates a doubled and a tripled voltage levels to supply the LCD ...

Page 273: ...0 C1 C2 LCON 1 Figure 17 1 Voltage Booster Block Diagram LCD Drive VLC1 VLC2 Voltage Booster VLC2 Voltage Regulator 1 05 V VLC0 COM0 3 SEG0 SEG31 CA CB CAB C2 C1 VLC1 C0 VLC0 LCD Drive VLC1 VLC2 Voltage Booster VLC2 Voltage Regulator 1 5 V VLC0 COM0 3 SEG0 SEG31 CA CB CAB C1 C0 VLC0 VLC1 VLC0 VLC0 1 2 Bias and Static 1 3 Bias Figure 17 2 Pin Connection Example ...

Page 274: ...oltage can be set by the software The criteria voltage can be set by matching to one of the 4 kinds of voltage below that can be used 2 2 V 2 4 V 3 0 V or 4 0 V VDD reference voltage or external input level External reference voltage The VLD block works only when VLDCON 2 is set If VDD level is lower than the reference voltage selected with VLDCON 1 0 VLDCON 3 will be set If VDD level is higher VL...

Page 275: ...a value to VLDCON an established resistor string is selected and the VVLD is fixed in accordance with this resistor Table 18 1 shows specific VVLD of 4 levels Voltage Level Detect Control F6H Set 1 Bank 1 R W Reset 00H 7 6 5 4 3 2 1 0 MSB LSB Not use Comparator M BANDGAP VLD Enable Disable VLDOUT Bias VREF VIN RVLD ExtRef Resistor String P2CONH 7 6 VBAT NOTES 1 The reset value of VLDCON is 00H 2 V...

Page 276: ...ented in tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics A C electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode Serial I O timing characteristics A D converter electrical characteristics ...

Page 277: ... active 60 Output current low IOL One I O pin active 30 Total pin current for port 100 Operating temperature TA 40 to 85 C Storage temperature TSTG 65 to 150 Table 19 2 D C Electrical Characteristics TA 40 C to 85 C VDD 1 8 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Operating voltage VDD fCPU 10 MHz 2 7 5 5 V fCPU 3 MHz 1 8 5 5 Input high voltage VIH1 All input pins except VIH2 0 8 VD...

Page 278: ...put pins 3 Output low leakage current ILOL VOUT 0 V All I O pins and output pins 3 Oscillator feed back resistors Rosc1 VDD 5 0 V TA 25 C XIN VDD XOUT 0 V 800 1000 1200 kΩ Pull up resistor RL1 VIN 0 V VDD 5 V 10 Port 0 1 2 3 4 5 TA 25 C 25 50 100 RL2 VIN 0 V VDD 5 V 10 TA 25 C RESET only 110 210 310 VLC0 out voltage Booster run mode VLC0 TA 25 C 1 3 bias mode 0 9 1 0 1 15 V TA 25 C 1 2 bias mode 1...

Page 279: ...tal oscillator 0 5 1 5 IDD3 Sub operating main osc stop VDD 3 V 10 32768 Hz crystal oscillator OSCCON 4 1 20 40 uA IDD4 Sub idle mode main osc stop VDD 3 V 10 32768 Hz crystal oscillator OSCCON 4 1 7 14 IDD5 Main stop mode sub osc stop VDD 5 V 10 1 3 VDD 3 V 10 0 5 2 NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 IDD1 and...

Page 280: ...ach other Table 19 3 D C Electrical Characteristics of S3C8248 C8245 TA 40 C to 85 C VDD 1 8 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Output high voltage VOH1 VDD 5 V IOH 1 mA All output pins except VOH2 VDD 1 0 V VOH2 VDD 5 V IOH 6 mA Port 3 0 only in S3C8248 C8245 VDD 0 7 Output low voltage VOL1 VDD 5 V IOL 2 mA All output pins except VOL2 0 4 VOL2 VDD 5 V IOH 12 mA Port 3 0 only ...

Page 281: ...ymbol Conditions Min Typ Max Unit Interrupt input high low width P0 0 P0 7 tINTH tINTL P0 0 P0 7 VDD 5 V 200 ns RESET input low width tRSL VDD 5 V 5 us NOTE User must keep more large value then min value tTIH tTIL 0 8 VDD 0 2 VDD 0 2 VDD Figure 19 1 Input Timing for External Interrupts Ports 0 tRSL 0 2 VDD RESET Figure 19 2 Input Timing for RESET ...

Page 282: ...ance CIO Table 19 6 Data Retention Supply Voltage in Stop Mode TA 40 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR 2 5 5 V Data retention supply current IDDDR VDDDR 2 V 3 uA Execution of STOP Instrction RESET Occurs VDDDR Stop Mode Oscillation Stabilization Time Normal Operating Mode Data Retention Mode tWAIT RESET VDD NOTE tWAIT is the same as 4096 x 1...

Page 283: ...ame as 16 x BT clock Figure 19 4 Stop Mode Main Release Timing Initiated by Interrupts Execution of STOP Instruction VDDDR Stop Mode Idle Mode Data Retention Mode tWAIT VDD Interrupt Normal Operating Mode Oscillation Stabilization Time 0 2 VDD NOTE When the case of select the fxx 128 for basic timer input clock before enter the stop mode tWAIT 128 x 16 x 1 32768 62 5 ms Figure 19 5 Stop Mode Sub R...

Page 284: ...f Top EOT 1 3 Offset Error of Bottom EOB 0 5 2 Conversion time 1 tCON 40 fxx Analog input voltage VIAN AVSS AVREF V Analog input impedance RAN 2 1000 MΩ Analog reference voltage AVREF 2 5 VDD V Analog ground AVSS VSS VSS 0 3 Analog input current IADIN AVREF VDD 5 V 10 uA Analog block current 2 IADC AVREF VDD 5 V 1 3 mA AVREF VDD 3 V 0 5 1 5 AVREF VDD 5 V When power down mode 100 500 nA NOTES 1 Con...

Page 285: ...C0 0 1 Regulated Voltage VLC0 ILC0 6 uA 1 2 bias 1 4 1 5 1 7 Booster Voltage VLC1 Connect 1 MΩ load between VSS and VLC1 2VLC0 0 1 2VLC0 0 1 VLC2 Connect 1 MΩ load between VSS and VLC2 Table 19 9 Characteristics of Voltage Level Detect Circuit TA 25 C Parameter Symbol Conditions Min Typ Max Unit Operating Voltage of VLD VDDVLD 1 8 5 5 V Voltage of VLD VVLD VLDCON 1 0 00b 2 05 2 2 2 35 V VLDCON 1 0...

Page 286: ... Parameter Symbol Conditions Min Typ Max Unit SCK Cycle time tCYC 200 ns Serial Clock High Width tSCKH 60 Serial Clock Low Width tSCKL 60 Serial Output data delay time tOD 50 Serial Input data setup time tID 40 Serial Input data Hold time tIH 100 Output Data Input Data SCK tSCKH tCYC tSCKL 0 8 VDD 0 2 VDD tOD tID tIH 0 8 VDD 0 2 VDD SI SO Figure 19 6 Serial Data Transfer Timing ...

Page 287: ... Table 19 12 Main Oscillator Clock Stabilization Time tST1 TA 40 C to 85 C VDD 4 5 V to 5 5 V Oscillator Test Condition Min Typ Max Unit Crystal VDD 4 5 V to 5 5 V 10 ms Ceramic Stabilization occurs when VDD is equal to the minimum oscillator voltage range 4 ms External clock XIN input high and low level width tXH tXL 50 500 ns NOTE Oscillation stabilization time tST1 is the time required for the ...

Page 288: ...19 7 Clock Timing Measurement at XIN Table 19 13 Sub Oscillator Frequency fOSC2 TA 40 C 85 C VDD 1 8 V to 5 5 V Oscillator Clock Circuit Test Condition Min Typ Max Unit Crystal C1 C2 XTIN XTOUT R Crystal oscillation frequency C1 22 pF C2 33 pF R 39 KΩ 32 32 768 35 kHz External Clock XTIN XTOUT XTIN input frequency 32 100 kHz ...

Page 289: ... mode VDD 3 0V to 5 5V 6 sec VDD 2 0V to 3 0V 2 sec External clock VDD 2 0V to 5 5V XTIN input high and low level width tXTH tXTL 5 15 usec NOTE Oscillation stabilization time tST2 is the time required for the oscillator to it s normal oscillation when stop mode is released by interrupts 10 MHz fCPU 3 MHZ 1 MHz 1 2 3 4 5 6 7 Supply Voltage V Minimum instruction clock 1 4 x oscillator frequency 5 5...

Page 290: ...249 microcontroller is currently available in 80 pin QFP TQFP package 80 QFP 1420C 80 20 00 0 20 23 90 0 30 14 00 0 20 17 90 0 30 1 0 80 0 35 0 10 NOTE Dimensions are in millimeters 0 15 MAX 0 80 0 15 0 10 0 05 0 8 0 10 MAX 0 80 0 20 0 05 MIN 2 65 0 10 3 00 MAX 0 80 0 20 Figure 20 1 Package Dimensions 80 QFP 1420C ...

Page 291: ...47 C8249 P8249 20 2 80 TQFP 1212 80 12 00 BSC 14 00 BSC 12 00 BSC 14 00 BSC 0 09 0 20 0 7 NOTE Dimensions are in millimeters 1 1 25 0 50 0 60 0 15 0 05 0 15 1 00 0 05 1 20 MAX 0 17 0 27 0 08 MAX M Figure 20 2 Package Dimensions 80 TQFP 1212 ...

Page 292: ...f the S3C8248 C8245 C8247 C8249 microcontroller It has an on chip OTP ROM instead of a masked ROM The EPROM is accessed by serial data format The S3P8245 P8249 is fully compatible with the S3C8248 C8245 C8247 C8249 both in function and in pin configuration Because of its simple programming requirements the S3P8245 P8249 is ideal as an evaluation chip for the S3C8248 C8245 C8247 C8249 ...

Page 293: ...A CB AVSS AVREF P2 7 ADC7 VVLDREF P2 6 ADC6 P2 5 ADC5 SEF26 P5 2 SEG27 P5 3 SEG28 P5 4 SEG29 P5 5 SEG30 P5 6 SEG31 P5 7 P3 0 TBPWM P3 1 TAOUT TAPWM P3 2 TACLK P3 3 TACAP SDAT P3 4 SCLK VDD VSS XOUT XIN VPP TEST XTIN XTOUT RESET P0 0 INT0 P0 1 INT1 P0 2 INT2 P0 3 INT3 P0 4 INT4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12...

Page 294: ... into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Option RESET RESET 19 I Chip Initialization VDD VSS VDD VSS 12 13 Logic power supply pin VDD should be tied to 5 V during programming Table 21 2 Comparison of S3P8245 P8249 and S3C8248 C8245 C8247 C8249 Features Characteristic S3P8245 P8249 S3C8248 C8245 C8247 C8249 Program Memory 16...

Page 295: ...ead 12 5 V 0 0000H 0 EPROM program 12 5 V 0 0000H 1 EPROM verify 12 5 V 1 0E3FH 0 EPROM read protection NOTE 0 means Low level 1 means High level Table 21 4 D C Electrical Characteristics TA 40 C to 85 C VDD 1 8 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Operating voltage VDD fCPU 10 MHz 2 7 5 5 V All input pins except VIH2 3 1 8 5 5 Input high VIH1 Port 4 5 VLCD2 VDD 0 8 VDD VDD volt...

Page 296: ...VOUT 0 V All I O pins and Output pins 3 Oscillator feed back resistors Rosc1 VDD 5 0 V TA 25 C XIN VDD XOUT 0 V 800 1000 1200 kΩ Pull up resistor RL1 VIN 0 V VDD 5 V 10 Port 0 1 2 3 4 5 TA 25 C 25 50 100 RL2 VIN 0 V VDD 5 V 10 TA 25 C RESET only 110 210 310 VLC0 out voltage Booster run mode VLC0 TA 25 C 1 3 bias mode 0 9 1 0 1 15 V TA 25 C 1 2 bias mode 1 4 1 5 1 7 VLC1 out voltage Booster run mod...

Page 297: ...rystal oscillator 0 5 1 5 IDD3 Sub operating main osc stop VDD 3 V 10 32768 Hz crystal oscillator OSCCON 4 1 20 40 uA IDD4 Sub idle mode main osc stop VDD 3 V 10 32768 Hz crystal oscillator OSCCON 4 1 7 14 IDD5 Main stop mode sub osc stop VDD 5 V 10 1 3 VDD 3 V 10 0 5 2 NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 IDD a...

Page 298: ...VDD 1 8 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Output high voltage VOH1 VDD 5 V IOH 1 mA All output pins except VOH2 VDD 1 0 V VOH2 VDD 5 V IOH 6 mA Port 3 0 only in S3P8245 VDD 0 7 Output low voltage VOL1 VDD 5 V IOL 2 mA All output pins except VOL2 0 4 VOL2 VDD 5 V IOH 12 mA Port 3 0 only in S3P8245 0 7 10 MHz fCPU 3 MHZ 1 MHz 1 2 3 4 5 6 7 Supply Voltage V Minimum instruction c...

Page 299: ...S3P8245 P8249 OTP S3C8248 C8245 P8245 C8247 C8249 P8249 21 8 NOTES ...

Page 300: ...ng Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM88 The SASM88 is a relocatable a...

Page 301: ...22 2 BUS SMDS2 RS 232C POD Probe Adapter PROM OTP Writer Unit RAM Break Display Unit Trace Timer Unit SAM8 Base Unit Power Supply Unit IBM PC AT or Compatible TB8249 Target Board EVA Chip Target Application System Figure 22 1 SMDS Product Configuration SMDS2 ...

Page 302: ...8245 C8247 C8249 microcontroller It is supported with the SMDS2 TB8245 8249 SM1317A GND V CC Idle Stop J101 50 Pin Connector 2 1 39 40 50 Pin Connector 42 41 79 80 100 Pin Connector 25 1 RESET 7411 144 QFP S3E8240 EVA Chip J102 XI MDS XTAL To User_VCC Off On Device Selection 8245 8249 Figure 22 2 TB8245 8249 Target Board Configuration ...

Page 303: ... the target board evaluation chip The target system must have its own power supply NOTE The following symbol in the To User_Vcc Setting column indicates the electrical short off configuration Table 22 2 Main clock Selection Settings for TB8245 9 Sub Clock Settings Operating Mode Comments XIN XTAL MDS No Connection SMDS2 SMDS2 100 Pin Connector EVA Chip S3E8240 XIN XOUT Set the XI switch to MDS whe...

Page 304: ...S2 SELECTION SAM8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 22 4 The SMDS2 Tool Selection Setting SW1 Setting Operating Mode SMDS2 SMDS2 Target System R W R W SMDS2 IDLE LED The Yellow LED is ON when the evaluation chip S3E...

Page 305: ... 30 32 34 36 38 40 40 Pin DIP Connector J102 P2 5 ADC5 P2 7 ADC7 V VLDREF AVSS CA VLC1 COM0 COM2 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 P5 0 P2 6 ADC6 AVREF CB VLC0 VLC2 COM1 COM3 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 P5 1 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 ...

Page 306: ...applicable See ROM Selection Form Customer sample Risk order See Risk Order Sheet Please answer the following questions For what kind of product will you be using this order New product Upgrade of an existing product Replacement of an existing product Other If you are replacing an existing product please indicate the former product name What are the main reasons you decided to use a Samsung microc...

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Page 308: ... Package Number of Pins ____________ Package Type _____________________ Intended Application ________________________________________________________________ Product Model Number ________________________________________________________________ Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated below We believe our risk order product to be ...

Page 309: ......

Page 310: ...chment Check one Diskette PROM Customer Checksum ________________________________________________________________ Company Name ________________________________________________________________ Signature Engineer ________________________________________________________________ Please answer the following questions Application Product Model ID _______________________ Audio Video Telecom LCD Databank ...

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Page 312: ... Dates and Quantity ROM Code Release Date Required Delivery Date of Device Quantity Please answer the following questions What is the purpose of this order New product development Upgrade of an existing product Replacement of an existing microcontroller Other If you are replacing an existing microcontroller please indicate the former microcontroller name What are the main reasons you decided to us...

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Page 314: ...ead Protection 1 Yes No Please answer the following questions Are you going to continue ordering this device Yes No If so how much will you be ordering _________________pcs Application Product Model ID _______________________ Audio Video Telecom LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation Remocon Other Please describe in detail its application _____________________...

Page 315: ...BOOK SPINE TEXT SAMSUNG Logo S3C8248 C8245 P8245 C8247 C8249 P8249 Microcontrollers User s Manual Rev 3 March 2002 ...

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