
INSTRUCTION SET
S3C8248/C8245/P8245/C8247/C8249/P8249
6-18
BCP
—
Bit Compare
BCP
dst,src.b
Operation:
dst(0) – src(b)
The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both
operands are unaffected by the comparison.
Flags:
C:
Unaffected.
Z:
Set if the two bits are the same; cleared otherwise.
S:
Cleared to "0".
V:
Undefined.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst src
opc
dst | b | 0
src
3
6
17
r0
Rb
NOTE
: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H and register 01H = 01H:
BCP
R1,01H.1
→
R1 = 07H, register 01H = 01H
If destination working register R1 contains the value 07H (00000111B) and the source register
01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of
the source register (01H) and bit zero of the destination register (R1). Because the bit values are
not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).
Summary of Contents for C8245
Page 31: ...ADDRESS SPACES S3C8248 C8245 P8245 C8247 C8249 P8249 2 20 NOTES ...
Page 107: ...INTERRUPT STRUCTURE S3C8248 C8245 P8245 C8247 C8249 P8249 5 18 NOTES ...
Page 195: ...INSTRUCTION SET S3C8248 C8245 P8245 C8247 C8249 P8249 6 88 NOTES ...
Page 221: ...I O PORTS S3C8248 C8245 P8245 C8247 C8249 P8249 9 16 NOTES ...
Page 245: ...16 BIT TIMER 0 1 S3C8248 C8245 P8245 C8247 C8249 P8249 12 10 NOTES ...
Page 249: ...WATCH TIMER S3C8248 C8245 P8245 C8247 C8249 P8249 13 4 NOTES ...
Page 267: ...A D CONVERTER S3C8248 C8245 P8245 C8247 C8249 P8249 15 6 NOTES ...
Page 299: ...S3P8245 P8249 OTP S3C8248 C8245 P8245 C8247 C8249 P8249 21 8 NOTES ...
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