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FPGA35S6046/FPGA35S6101 User’s Manual
5.6
Digital I/O
The FPGA35S6 digital I/O on connector CN9 uses the circuitry shown below to level shift the input voltage from 5V to 3.3V allowing the I/O to
be 5V tolerant.
Figure 7: CN9 Digital I/O Circuitry
5.7
RS-232/422/485 Transceivers
The RS-232/422/485 transceivers on this board all it to interface with a variety of serial port standards, incremental encoders, and other
devices. The transceivers are highly configurable from the FPGA fabric. The Figure below shows the connections between the FPGA signals,
the Exar SP338 transceiver, and the connector.
Figure 8: Serial Port Transceiver
Xilinx
Spartan 6
Level Shifter
D
ig
ita
l I
/O
CN4/CN9
33Ω
10KΩ
+5V/3.3V
