rtd FPGA35S6 Series, User Manual

Page: 19 / 37

RTD Embedded Technologies, Inc.
| www.rtd.com 19 FPGA35S6046/FPGA35S6101 User’s Manual
P3 is attached to Bank 0, and support any of the Spartan 6 I/O Standards that use a 3.3V V
CCO
and no reference voltage. This includes
LVTTL, LVCMOS33, and LVDS_33 input and output.
Connector P3 also provides a connection to the Xilinx JTAG programming header. This connector header mates with the Xilinx OEM
programming cable through an adapter cable. The adapter cable is provided when purchasing the Starter Kit.
Table 13: P3 Pin Assignments
IDAN P3 Pin
Signal
Pull
Jmpr C9 Pin
Row 1 Row 2 Row 3
1 port1_p[0]
JP4
1
22 GND 2
43 port1_n[0] 3
2 GND 4
23 port1_p[1] 5
44 GND 6
3 port1_n[1] 7
24 GND 8
45 port1_p[2] 9
4 GND 10
25 port1_n[2] 11
46 GND 12
5 port1_p[3] 13
26 GND 14
47 port1_n[3] 15
6 GND 16
27 port1_p[4]
JP5
17
48 GND 18
7 port1_n[4] 19
28 GND 20
49 port1_p[5] 21
8 GND 22
29 port1_n[5] 23
50 GND 24
9 port1_p[6] 25
30 GND 26
51 port1_n[6] 27
10 GND 28
31 port1_p[7] 29
52 GND 30
11 port1_n[7] 31
32 GND 32
53 port1_p[8]
JP6
33
12 GND 34
33 port1_n[8] 35
54 GND 36
13 port1_p[9] 37
34 GND 38
55 port1_n[9] 39
14 GND 40
35 port1_p[10] 41
56 GND 42
15 port1_n[10] 43
36 GND 44
57 port1_p[11] 45
16 GND 46
37 port1_n[11] 47
58 GND 48
17 +5V 49
38 GND 50
59 Reserved
18 jtag_vref CN3.2
39 GND CN3.3