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FPGA35S6046/FPGA35S6101 User’s Manual
4.3
Connectors and Jumpers
P2: RS-232/422/485 Transceiver Connector
Connector Part #:
Adam Tech DE37SD
Mating Connector:
Adam Tech DE37PD
Connector P2 provides configurable RS-232/422/485 transceivers. The pin configuration and associated FPGA signals are shown in the Table
below. The signal names reflect the signal names in the Xilinx UCF file with the device pin out. For other modes, and information on how to
configure the port, see Section 5.7 on page 25.
These signals are attached to Bank 2 of the FPGA, and should be configured as LVCMOS33.
Table 12: P2 Pin Assignments
IDAN P2 Pin
RS-232 Signal
Board Pin
Row 1
Row 2
1
com1_dcd
CN10.1
20
com1_dsr
CN10.2
2
com1_rxd
CN10.3
21
com1_rtd
CN10.4
3
com1_txd
CN10.5
22
com1_cts
CN10.6
4
com1_dtr
CN10.7
23
com1_ri
CN10.8
5
GND
CN10.9
24
com2_dcd
CN11.1
6
com2_dsr
CN11.2
25
com2_rxd
CN11.3
7
com2_rtd
CN11.4
26
com2_txd
CN11.5
8
com2_cts
CN11.6
27
com2_dtr
CN11.7
9
com2_ri
CN11.8
28
GND
CN11.9
10
com3_dcd
CN12.1
29
com3_dsr
CN12.2
11
com3_rxd
CN12.3
30
com3_rtd
CN12.4
12
com3_txd
CN12.5
31
com3_cts
CN12.6
13
com3_dtr
CN12.7
32
com3_ri
CN12.8
14
GND
CN12.9
33
com4_dcd
CN13.1
15
com4_dsr
CN13.2
34
com4_rxd
CN13.3
16
com4_rtd
CN13.4
35
com4_txd
CN13.5
17
com4_cts
CN13.6
36
com4_dtr
CN13.7
18
Com4_ri
CN13.8
37
GND
CN13.9
19
n.c.
n.c.
P3: Digital I/O Connector
Connector Part #:
VALCONN HDB-62S
Mating Connector:
VALCONN HDB-62P
Connector P3 provides 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are controlled by
jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the Xilinx UCF file with
the device pin out.
