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14
FPGA35S6046/FPGA35S6101 User’s Manual
CN9: Digital I/O Connector
Connector CN9 provides 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are controlled by
jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names in the Xilinx UCF file with the
device pin out.
CN9 is attached to Bank 0, and supports any of the Spartan 6 I/O Standards that use a 3.3V V
CCO
and no reference voltage. This includes
LVTTL, LVCMOS33, and LVDS_33 input and output.
Table 6: CN9 I/O Pin Assignments
GND
2
1
port1_p[0]
JP4
GND
4
3
port1_n[0]
GND
6
5
port1_p[1]
GND
8
7
port1_n[1]
GND
10
9
port1_p[2]
GND
12
11
port1_n[2]
GND
14
13
port1_p[3]
GND
16
15
port1_n[3]
GND
18
17
port1_p[4]
JP5
GND
20
19
port1_n[4]
GND
22
21
port1_p[5]
GND
24
23
port1_n[5]
GND
26
25
port1_p[6]
GND
28
27
port1_n[6]
GND
30
29
port1_p[7]
GND
32
31
port1_n[7]
JP6
GND
34
33
port1_p[8]
GND
36
35
port1_n[8]
GND
38
37
port1_p[9]
GND
40
39
port1_n[9]
GND
42
41
port1_p[10]
GND
44
43
port1_n[10]
GND
46
45
port1_p[11]
GND
48
47
port1_n[11]
GND
50
49
+5V
CN10, CN11, CN12, CN13: RS-232/422/485 Transceiver Connectors
These connectors each provide configurable RS-232/422/485 transceivers. The pin configuration and associated FPGA signals are shown in
the Table below. For other modes, and information on how to configure the port, see Section 5.7 on page 25. The signal names reflect the
signal names in the Xilinx UCF file with the device pin out.
CN10 is associated with the “com1” signals, CN11 with the “com2” signals, CN12 with the “com3” signals, and CN13 with the “com4” signals.
These signals are attached to Bank 2 of the FPGA, and should be configured as LVCMOS33.
Table 7: CN10, CN11, CN12, CN13 I/O Pin Assignments
com?_dsr (RX)
2
1
com?_dcd (RX)
com?_rtd (TX)
4
3
com?_rxd (RX)
com?_cts (RX)
6
5
com?_txd (TX)
com?_ri (RX)
8
7
com?_dtr (TX)
GND
10
9
GND
