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FPGA35S6046/FPGA35S6101 User’s Manual
4.3.1
B
US
C
ONNECTORS
CN1(Top) & CN2(Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the
PCI/104-Express
Specification
. (See PC/104 Specifications on page 35)
The FPGA35S6
is a “Universal” board, and can connect to either a Type 1 or
Type 2 PCIe/104 connector.
4.3.2
J
UMPERS
JP4, JP5, JP6: Pull up/Pull down Jumper
JP4, JP5, and JP6 are 3-pin two position jumpers that are used to set pull up or pull downs options on the I/O signal lines of CN9. Refer to
Table 13 to determine which I/O pins are effected by each jumper.
Table 15: Pull up/Pull down Jumper options
Setting
Description
1-2
I/O is pulled up to 3.3V or 5V (Set by B1 and B2)
2-3
I/O is pulled down to GND
No Jumper I/O has no pull up/pull down
JP1: Embedded Programmer Enable
This jumper is used to enable the embedded programmer to the JTAG chain. See Section 5.8 on page 26 for more details. The board can be
programmed from and external programmer with this jumper in either position.
Table 16: JP1
–
Embedded Programmer Enable
Setting
Description
1-2
Enabled embedded programmer
2-3 or
open
Disables embedded programmer
JP8: User ID Jumper
The User ID Jumper is a four position, user defined jumper block. The jumpers can be read by the FPGA. An installed jumper results in a logic
low, and an open jumper results in a logic high.
Table 17: JP8
–
User ID Jumper
Position
Description
1-2
User ID bit 0
3-4
User ID bit 1
5-6
User ID bit 2
7-8
User ID bit 3
4.3.3
S
OLDER
J
UMPER
B2: Pull up Voltage
Solder jumper B2 is used to set the pull up voltage for JP4, JP5 and JP6.
Table 18: B2 Pull up Voltage
Setting Description
1-2
Sets Pull up voltage to 3.3V
2-3
Sets Pull up voltage to 5V
