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FPGA35S6046/FPGA35S6101 User’s Manual
5
Functional Description
5.1
Block Diagram
The Figure below shows the functional block diagram of the FPGA35S6. The various parts of the block diagram are discussed in the following
sections.
Figure 6: FPGA35S6 Block Diagram
5.2
Configuration Flash
The FPGA35S6 includes a Configuration Flash that is sized for the FPGA. At power up, the FPGA design is loaded from the Configuration
Flash. The Configuration Flash can be programmed through either the Embedded Digilent® USB JTAG Programmer, or CN3: Xilinx JTAG
Programming Header.
5.3
Oscillator
The FPGA35S6 features a 27Mhz oscillator for clock based operations in the FPGA.
5.4
EEPROM
The FPGA35S6 features a 256 x 16 SPI EEPROM, ATMEL AT93C66A. For information on the AT93C66A refer to
5.5
DDR2 SRAM
The FPGA35S6 features a 1Gb DDR2 SRAM, MT47H64M16HR 25E. This is interface to the Spartan 6 FPGA using Xilinx Memory Interface
Generators (MIG) core. The example FPGA code has demonstrated how to use this core in a FPGA design.
PC
Ie
Bu
s
PCIe x1
Link
Xilinx
Spartan 6
Oscillator
RS-232/422/485
Transceivers
C
N
10
, C
N
11,
C
N
12
, C
N
13
DDR2 SRAM
H
igh
Sp
ee
d D
igital I/O C
N
8
EEPROM
Level Shifter
D
igital I/O C
N
9
