51
The following table lists signals of the AT portion of the PC/104 bus.
Notes:
ISA bus refresh is not supported by this cpuModule.
Keying pin positions have the pin cut on the bottom of the board and the hole plugged in the con-
nector to prevent misalignment of stacked modules. This is a feature of the PC/104 specification and
should be implemented on all mating PC/104 modules.
Signals marked with (*) are active-low.
All bus lines can drive a maximum current of 4 mA at TTL voltage levels.
PC/104 AT Bus Connector,
P4 or CN1
Pin
Row C
Row D
0
0V
0V
1
SBHE*
MEMCS16*
2
LA23
IOCS16*
3
LA22
IRQ10
4
LA21
IRQ11
5
LA20
IRQ12
6
LA19
IRQ15
7
LA18
IRQ14
8
LA17
DACK0*
9
MEMR*
DRQ0
10
MEMW*
DACK5*
11
SD8
DRQ5
12
SD9
DACK6*
13
SD10
DRQ6
14
SD11
DACK7*
15
SD12
DRQ7
16
SD13
+5V*
17
SD14
MASTER*
18
SD15
0V
19
(Keying pin)
0V
Summary of Contents for cpuModule CMC6686GX
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Page 35: ...34 CMC6686GX Connector Locations...
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Page 104: ...103 Default Jumper Settings JP2 2 pin jumper Open no termination...
Page 105: ...104 Solder Jumpers Solder jumpers are set at the factory and are rarely changed...
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