AN101
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11 July 2019
Page 19 of 27
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Write 0x07 (7d) to Tap Threshold Low register (TTL). This register represents the 8-bit (0d
–
255d) jerk low threshold to determine if a tap is detected. The Performance Index (PI) is the
jerk signal that is expected to be greater than this threshold and less than the TTH threshold
during single and double tap events.
This step is optional as this is also a default setting. This
setting can be adjusted as needed.
Register Name
Address
Value
TTL
0x2D
0x07
-
Write 0xA2 (162d) to set the FTD counter register to 0.005 seconds. This register contains
counter information for the detection of
any
tap event. A tap event must be above the
performance index threshold for at least the low limit (FTDL0
– FTDL2) and no more than the
high limit (FTDH0
– FTDH4).
This step is optional as this is also a default setting. This setting
can be adjusted as needed.
Register Name
Address
Value
FTD
0x2E
0xA2
-
Write 0x24 (36d) to set the STD counter register to 0.09 seconds. This register contains
counter information for the detection of a
double
tap event. This register sets the total amount
of time that the two taps in a double tap event can be above the PI threshold (TTL).
This step
is optional as this is also a default setting.
This setting can be adjusted as needed.
Register Name
Address
Value
STD
0x2F
0x24
-
Write 0x28 (40d) to set the TLT counter register to 0.1 seconds. This register contains counter
information for the detection of a tap event. This register sets the total amount of time that the
tap algorithm will count samples that are above the PI threshold (TTL) during a potential tap
event. It is used during both single and double tap events. However, reporting of single taps
on the physical interrupt pin INT1 or INT2 will occur at the end of the TWS.
This step is
optional as this is also a default setting
. This setting can be adjusted as needed.
Register Name
Address
Value
TLT
0x30
0x28
-
Write 0xA0 (160d) to set the TWS counter register to 0.4 seconds. This register contains
counter information for the detection of single and double taps. This counter defines the time
window for the entire tap event, single or double, to occur. Reporting of single taps on the
physical interrupt pin INT1 or INT2 will occur at the end of this tap window.
This step is
optional as this is also a default setting.
This setting can be adjusted as needed.
Register Name
Address
Value
TWS
0x31
0xA0
