AN101
© Kionix 2019 All Rights Reserved
11 July 2019
Page 20 of 27
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Write 0x30 to Interrupt Control Register (INC1) to output the physical interrupt of the
previously defined Tap/Double-Tap function. This value will create an active high and latched
interrupt.
Register Name
Address
Value
INC1
0x22
0x30
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Write 0x04 to Interrupt Control Register 4 (INC4) to set the Tap/Double-Tap interrupt (TDTI)
to be reported on physical interrupt pin INT1.
Register Name
Address
Value
INC4
0x25
0x04
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Write 0xC4 to Control Register 1 (CNTL1) to set the accelerometer in operating mode, high
performance (full power), G-range to ±8g, and enable the Directional Tap function.
Register Name
Address
Value
CNTL1
0x1B
0xC4
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Monitor the physical interrupt INT1 of the accelerometer, if the acceleration input profile
satisfies the criteria previously established for Tap/Double-Tap, then there should be a
positive latched interrupt present. Also, the interrupt would be reflected in bit 4 of
STATUS_REG (INT bit), and bit 3 and bit 2 of INS2 registers. To distinguish between a single
and double-tap events, monitor INS2 register bits <TDTS1:TDTS0>. TDTS1 bit3 would be set
for Double-tap event, and TDTS0 bit2 for Single-tap event. Also, INS1 register can be
monitored to identify the direction the tap came from.
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Read Interrupt Latch Release (INT_REL) register to unlatch (clear) the output interrupt
created by the Tap/Double-Tap detection function. The read value is dummy.
Register Name
Address
Value
INT_REL
0x1A
N/A
