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AN101 

 

 

 

© Kionix 2019 All Rights Reserved 

11 July 2019 

Page 17 of 27 

                            

 

 

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Write  0x30  to  Interrupt  Control  Register  (INC1)  to  output  the  physical  interrupt  of  the 
previously  defined  Tilt  Position  function.  This  value  will  create  an  active  high  and  latched 
interrupt.  
 

Register Name 

Address 

Value 

INC1 

0x22 

0x30 

 

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Write 0x01 to Interrupt Control Register 4 (INC4) to set the Tilt Position interrupt (TPI1) to be 
reported on physical interrupt pin INT1. 
 

Register Name 

Address 

Value 

INC4 

0x25 

0x01 

 

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Write  0xC1  to  Control  Register  1  (CNTL1) to set  the  accelerometer  in  operating  mode,  high 
performance (full power), G-range to ±8g, and enable the Tilt Position function. 

 

Register Name 

Address 

Value 

CNTL1 

0x1B 

0xC1 

 

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Monitor the physical interrupt INT1 of the accelerometer. If changes in the tilt position satisfies 
the  criteria  previously  established,  then  there  should  be  a  positive  latched  interrupt  present. 
Also,  the interrupt would be reflected in bit 4 of STATUS_REG (INT bit),  bit 0 of INS2  (TPS 
bit), and Current Tilt Position register TSCP as well as Previous Tilt Position register TSPP.  
 

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Read  Interrupt  Latch  Release  (INT_REL)  register  to  unlatch  (clear)  the  output  interrupt 
created by the Tilt Position function. The read value is dummy. 

 

Register Name 

Address 

Value 

INT_REL 

0x1A 

N/A 

 

 

3.6.2.

 

  Face Detect Position 

 

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As was noted above, the current orientation of the sensor can be read from TSCP register at 
any time. Assuming tilt detection was not changed from its default setting (detect positive and 
negative directions of all three axes (+x,  -x, +y,  -y, +z,  -z)),  one of the bits in TSCP register 
will be set to 1 to indicate the current orientation of the sensor. 

 
 
 
 
 

 

Summary of Contents for Kionix KX134

Page 1: ...ensure that our accelerometers will meet design expectations by default but it is not possible to provide default setting to work in every environment Depending on the intended application it is very...

Page 2: ...pers refine their application requirements 3 1 Asynchronous Reading This example configures and enables the accelerometer to start outputting sensor data that can be asynchronously read from the outpu...

Page 3: ...he latched interrupt will auto clear by default Register Name Address Value INC1 0x22 0x30 Write 0x10 to Interrupt Control 4 INC4 to set the Data Ready interrupt to be reported on physical interrupt p...

Page 4: ...et the Output Data Rate ODR of the accelerometer to 50 Hz This step is optional as this is also a default setting Register Name Address Value ODCNTL 0x21 0x06 Write 0xE0 to Control 1 CNTL1 to set the...

Page 5: ...Write 0x40 to Interrupt Control 4 INC4 to set the Buffer Full interrupt to be reported on physical interrupt pin INT1 Register Name Address Value INC4 0x25 0x40 Write 0xE0 to Buffer Control 2 BUF_CNTL...

Page 6: ...er Name Address Value ODCNTL 0x21 0x06 Write 0x30 to Interrupt Control INC1 to enable physical interrupt pin INT1 set the polarity of the physical interrupt to active high and configure for latched op...

Page 7: ...ta can be captured both before and after an event external trigger tap wakeup freefall Write 0x00 to Control 1 CNTL1 to set the accelerometer in stand by mode Register Name Address Value CNTL1 0x1B 0x...

Page 8: ...d set the output data rate for the back to sleep engine to its default of 0 781Hz Register Name Address Value CNTL4 0x1E 0x60 Write 0x01 to Control 5 CNTL5 to put the sensor into sleep mode MAN_SLEEP...

Page 9: ...a which corresponds to 86 unique acceleration data samples The data set will include all the data prior to the trigger event plus all the data after the event 3 4 4 Buffer Reading Tips a The accelerat...

Page 10: ...e high and configure for latched operation Register Name Address Value INC1 0x22 0x30 Write 0x02 to Interrupt Control 4 INC4 to set the Wakeup Function Interrupt WUFI1 1 to be reported on physical int...

Page 11: ...ter Name Address Value WUFTH 0x49 0x20 BTSWUFTH 0x4A 0x00 Write 0xE0 to Control 1 CNTL1 to set the accelerometer into operating mode PC1 1 full power mode RES 1 data ready enabled DRDYE 1 range to 8g...

Page 12: ...WUFS bit in the Interrupt Status 3 INS3 Register Name Address Value INT_REL 0x1A N A Write 0x01 to Control 5 CNTL5 to force sleep state MAN_SLEEP 1 With Back to Sleep engine disabled this step is requ...

Page 13: ...ure for latched operation Register Name Address Value INC1 0x22 0x30 Write 0x0A to Interrupt Control 4 INC4 to set the Back to Sleep Interrupt BTSI 1 and Wakeup Interrupt WUFI1 to be reported on physi...

Page 14: ...a Wake up interrupt is triggered The following formula is used WUFC counts Desired Delay Time sec x OWUF Hz WUFC counts 0 1 sec x 50 Hz 5 counts Register Name Address Value WUFC 0x4D 0x05 Write 0x80...

Page 15: ...A N A Continue to monitor the physical interrupt INT1 of the accelerometer if the lack of acceleration input profile satisfies the criteria previously established for the 0 5g of no motion detect thre...

Page 16: ...register Here we assume an 80 msec timer will be sufficient Note that each count value written to this register is calculated as 1 Tilt Position ODR 1 12 5Hz 80 msec Register Name Address Value TILT_...

Page 17: ...terrupt INT1 of the accelerometer If changes in the tilt position satisfies the criteria previously established then there should be a positive latched interrupt present Also the interrupt would be re...

Page 18: ...ue TDTRC 0x2A 0x03 Write 0x78 to Tap Double Tap Counter register TDTC to set the counter to 0 3 sec The TDTC counts starts at the beginning of the fist tap and it represents the minimum time separatio...

Page 19: ...tal amount of time that the two taps in a double tap event can be above the PI threshold TTL This step is optional as this is also a default setting This setting can be adjusted as needed Register Nam...

Page 20: ...function Register Name Address Value CNTL1 0x1B 0xC4 Monitor the physical interrupt INT1 of the accelerometer if the acceleration input profile satisfies the criteria previously established for Tap Do...

Page 21: ...ts 0 0625 g count 0 5 g Register Name Address Value FFTH 0x32 0x08 Write 0x04 to Free Fall Counter Register FFC to set the Free fall delay detection to 0 320 sec Note that the period of the free fall...

Page 22: ...atisfies the criteria previously established for the 0 5g free fall detect threshold level in both positive and negative directions of the X Y Z axis for more than 0 320 second then there should be a...

Page 23: ...in Control Register 1 is asserted it takes from 2 ms to 1300 ms depending on the ODR and Power Mode setting before the acceleration outputs are valid See the relevant Product Specification for detail...

Page 24: ...ister must be read in order to clear the physical interrupt pin This will also clear the Interrupt Source Registers and the INT bit 0x10 in the Status Register Microcontroller GPIO Interrupt Handling...

Page 25: ...WUFE bit in Control Register 4 Make sure that the Back to Sleep engine is enabled BTSE bit in Control Register 4 If Back to Sleep function is not used BTSE bit in Control Register 3 left at 0 the sle...

Page 26: ...nt effect on tap double tap direction resolution If tap detection is desired the part should be placed as far away from the edges of the device housing as possible with the ideal location being at the...

Page 27: ...ing Automatic sleep mode Step counting pedometer 9 Theory of Operation Kionix MEMS linear tri axis accelerometers function on the principle of differential capacitance Acceleration causes displacement...

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