AN101
© Kionix 2019 All Rights Reserved
11 July 2019
Page 24 of 27
5.
Interrupt Configuration
The physical interrupt has 6 possible configurations, based on two states for each of the three
customizable variables located in Interrupt Control Register 1:
Latched/Pulsed (IEL
– bit 3 – 0x08)
0
– Latched mode – When an interrupt is triggered, it will remain active on the pin until
cleared.
1
– Pulse mode – When an interrupt is triggered, it will cause a short (~50µs) pulse on the
pin and clear itself.
Polarity (IEA
– bit 4 – 0x10)
0
– Active Low – The interrupt pin will normally be HIGH, but will transition to LOW when
an interrupt is triggered.
1
– Active High – The interrupt pin will normally be LOW, but will transition to HIGH when
an interrupt is triggered.
Enable/Disable (IEN
– bit 5 – 0x20)
0
– Disabled – Interrupt conditions will not be reflected on the physical interrupt pin.
1
– Enabled – Interrupt conditions will be reflected on the physical interrupt pin.
5.1.
A Few Interrupt Tips
Read the Interrupt Release Register to Clear
In latched mode, the INT_REL register must be read in order to clear the physical interrupt
pin. This will also clear the Interrupt Source Registers and the INT bit (0x10) in the Status
Register.
Microcontroller/GPIO Interrupt Handling
–
GPIO configuration is based solely on the connected hardware. The accelerometers in
this family can be configured to issue interrupts depending on how the GPIO is
programmed to catch them (if this is not the case, please contact your Kionix Sales
Representative). Generally, when an interrupt is triggered, the developer should take the
following steps:
1- Disable GPIO interrupt
2- Clear GPIO interrupt and generate desired functionality
3- Enable GPIO interrupt
These steps should be taken without calling any digital communication transactions if
done in an interrupt context, because the operating system or kernel will not allow busy-
waiting on an I/O operation during an interrupt service routine.
Interrupt Polling - If physical interrupts are not used, a polling mechanism can be devised, which
checks the INT bit in STATUS_REG. This mechanism should then look at INS2 to determine
which engine caused the interrupt and what steps should be taken before clearing the interrupt
source information by reading the INT_REL register.
