AN101
© Kionix 2019 All Rights Reserved
11 July 2019
Page 9 of 27
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Write 0xE0 to Control 1 (CNTL1) to set the accelerometer into operating mode (PC1=1), full
power mode (RES=1), data ready enabled (DRDYE=1), range to ±8g (GSEL=0).
Register Name
Address
Value
CNTL1
0x1B
0xE0
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Provide some time for the buffer to fill to the configured threshold. Assuming the default ODR
was used, it should take approximately 0.86 seconds. After this time, trigger a wakeup event
by shaking the unit above the configured threshold and timing settings. Next, wait for the
Buffer-Full Interrupt. Once Buffer-Full Interrupt is issued on INT1 pin, acceleration data can
then be read from the Buffer Read (BUF_READ) register at address 0x63
in 2’s complement
format. Since the resolution of the samples data was set to 16-bit, both high and low bytes of
each sample were stored in the buffer, and recorded in the following order: X_L, X_H, Y_L,
Y_H, Z_L, Z_H with the oldest data point read first as it is a FIFO buffer. The full buffer
contains 516 bytes of data, which corresponds to 86 unique acceleration data samples. The
data set will include all the data prior to the trigger event, plus all the data after the event.
3.4.4.
Buffer Reading Tips
a) The acceleration data can be read from a buffer using multiple-byte read as shown in the
Figure 2 below. The register auto-increment feature is disabled when data is read from the
Buffer Read register.
b) If data is read using single-byte read, it should be read in increments of 3 bytes in 8-bit
resolution mode and 6 bytes in 16-bit resolution mode.
c) It is very important to follow proper I2C Write-Read sequence as specified in the product
specifications. More specifically, the Master should avoid sending the Stop (P) bit at the
end of the I2C Write command, and should issue a Repeat Start bit (Sr) at the start of the
I2C Read command as show in the Figure 2. Failure of following this sequence may result
in reading the same value from the Read Buffer.
Term
Definition
S
Start Condition
Sr
Repeated Start Condition
SAD
Slave Address
W
Write Bit
R
Read Bit
ACK
Acknowledge
NACK
Not Acknowledge
RA
Register Address
Data
Transmitted/Received Data
P
Stop Condition
Figure 2:
Proper I2C Sequence to Receive Data from the Slave
