RX Family
ADC Module Using Firmware Integration Technology
R01AN1666EJ0220 Rev. 2.20
Page 40 of 74
Dec 01, 2016
ADC_TRIG_SYNC_TRG4AN_OR_UDF4N =
5
,
// MTU4 TRGA or MTU4 underflow
//(complementary PWM mode)
ADC_TRIG_SYNC_TRG6AN =
6
,
// MTU6 TRGA
ADC_TRIG_SYNC_TRG7AN_OR_UDF7N =
7
,
// MTU7 TRGA or MTU7 underflow
//(complementary PWM mode)
ADC_TRIG_SYNC_TRG0EN =
8
,
// MTU0 TRGE
ADC_TRIG_SYNC_TRG4AN =
9
,
// MTU4 TADCORA
ADC_TRIG_SYNC_TRG4BN =
10
,
// MTU4 TADCORB
ADC_TRIG_SYNC_TRG4AN_OR_TRG4BN =
11
,
// MTU4 TADCORA or MTU4 TADCORB
ADC_TRIG_SYNC_TRG4AN_AND_TRG4BN =
12
,
// MTU4 TADCORA and MTU4 TADCORB
ADC_TRIG_SYNC_TRG7AN =
13
,
// MTU7 TADCORA
ADC_TRIG_SYNC_TRG7BN =
14
,
// MTU7 TADCORB
ADC_TRIG_SYNC_TRG7AN_OR_TRG7BN =
15
,
// MTU7 TADCORA or MTU7 TADCORB
ADC_TRIG_SYNC_TRG7AN_AND_TRG7BN =
16
,
// MTU7 TADCORA and MTU7 TADCORB
ADC_TRIG_SYNC_GTADTR0AN =
17
,
// GPT0 GTADTRA
ADC_TRIG_SYNC_GTADTR0BN =
18
,
// GPT0 GTADTRB
ADC_TRIG_SYNC_GTADTR1AN =
19
,
// GPT1 GTADTRA
ADC_TRIG_SYNC_GTADTR1BN =
20
,
// GPT1 GTADTRB
ADC_TRIG_SYNC_GTADTR2AN =
21
,
// GPT2 GTADTRA
ADC_TRIG_SYNC_GTADTR2BN =
22
,
// GPT2 GTADTRB
ADC_TRIG_SYNC_GTADTR3AN =
23
,
// GPT3 GTADTRA
ADC_TRIG_SYNC_GTADTR3BN =
24
,
// GPT3 GTADTRB
ADC_TRIG_SYNC_GTADTR0AN_OR_GTADTR0BN =
25
,
// GPT0 GTADTRA or GPT0 GTADTRB
ADC_TRIG_SYNC_GTADTR1AN_OR_GTADTR1BN =
26
,
// GPT1 GTADTRA or GPT1 GTADTRB
ADC_TRIG_SYNC_GTADTR2AN_OR_GTADTR2BN =
27
,
// GPT2 GTADTRA or GPT2 GTADTRB
ADC_TRIG_SYNC_GTADTR3AN_OR_GTADTR3BN =
28
,
// GPT3 GTADTRA or GPT3 GTADTRB
ADC_TRIG_SYNC_TMRTRG0AN =
29
,
// TMR0 TCORA
ADC_TRIG_SYNC_TMRTRG2AN =
30
,
// TMR2 TCORA
ADC_TRIG_SYNC_TPUTRGAN =
31
,
// TPUx TRGA
ADC_TRIG_SYNC_TPUTRG0AN =
32
,
// TPU0 TRGA
ADC_TRIG_SYNC_ELC =
48
,
// ELC
ADC_TRIG_SOFTWARE =
64
,
// software trigger; not for Group
// modes nor double trigger modes
// This is not set to TRSA or TRSB
ADC_TRIG_NONE =
0x3F
}
adc_trig_t;
typedef
struct
st_adc_cfg
{
adc_res_t resolution;
// 8, 10, or 12-bit
adc_align_t alignment;
// ignored if addition used
adc_add_t add_cnt;
// add or average samples
adc_clear_t clearing;
// clear after read
adc_trig_t trigger;
// default and Group A trigger source
adc_trig_t trigger_groupb;
// valid only for group modes
uint8_t priority;
// for S12ADIO int; 1=lo 15=hi 0=off/polled
uint8_t priority_groupb;
// S12GBADI interrupt priority; 0-15
}
adc_cfg_t;
/***** ADC_CONTROL() ARGUMENT DEFINITIONS *****/
typedef
enum
e_adc_cmd
{
// Commands for special hardware configurations
ADC_CMD_SET_DDA_STATE_CNT,
// for Disconnect Detection Assist
ADC_CMD_SET_SAMPLE_STATE_CNT,
// Command to configure channels, sensors, and comparator
ADC_CMD_ENABLE_CHANS,
// configure channels and sensors to scan