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Renesas mPD98431, User Manual

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CHAPTER  3   FUNCTIONAL  DESCRIPTION

User’s Manual  S14054EJ4V0UM

50

(c) Appending status information

The 

µ

PD98431 can append the status information of a packet to the receive data stream that is read from the

FIFO bus.  When the APSS bit of the MACC3 register is set to 1, the status information on the packet to be

read is prefixed to the receive data stream.  If the APSE bit of the MACC3 register is set to 1, the status

information is suffixed to the receive data stream.  The status information that is appended is the contents of

the RSVREG register that are updated each time a packet has been received.  These contents are

appended as 32-bit data.

(3) Timing for changing access direction of FIFO bus in 64-bit single bus mode

Figure 3-11 shows the timing for switching between reading receive data and writing transmit data in the 64-bit

single bus mode.  Be sure to deassert the FEN# signal once before switching the operation from reading to

writing or vice versa.

If the FEN# signal is deasserted during a write operation, detection of deasserting the FEN# signal to the next

rising edge of FCLK is assumed as valid writing.

If the FEN# signal is deasserted during a read operation, the valid data is output after detection of deasserting

the FEN# signal until the FCLK rises the next time.  If the data read last after the FEN# signal has been

deasserted is the intermediate data of the packet being read, however, the internal operation of the chip to read

data from the receive FIFO is not stopped by deasserting the FEN# signal.  Consequently, the rest of the data

cannot be correctly read when reading is resumed.  To avoid this, confirm the end of data by completely reading

the packet before deasserting the FEN# signal, or input the SKIP signal to set the FIFO bus in IDLE status and

then deassert the FEN# signal.

Summary of Contents for mPD98431

Page 1: ...ook over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1st 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ...

Page 2: ...ct for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and meas...

Page 3: ...User s Manual µ µ µ µPD98431 10 100 Mbps EthernetTM Controller Document No S14054EJ4V0UM00 4th edition Date Published July 2001 NS CP K Printed in Japan 1999 ...

Page 4: ...User s Manual S14054EJ4V0UM 2 MEMO ...

Page 5: ...evice inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND ...

Page 6: ...not be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific T...

Page 7: ...l deletion of descriptions in 3 4 1 3 Appending PAD p 47 Modification of description in 3 7 1 2 b SKIP signal pp 63 to 64 4 1 1 Port control register map Default value of the following registers modified CLRT MACC3 TIMR RIMR TSVREG1 TSVREG2 RSVREG FSVREG pp 66 to 93 4 2 Port Setting Registers Description of the following registers modified MACC1 CAR1 CAR2 CAM1 MACC3 TSVREG1 TSVREG2 RSVREG TFIC Bit...

Page 8: ...puters To understand the overall functions of the µPD98431 Read this manual in the order of CONTENTS Conventions Data significance Higher digits on the left and lower digits on the right Active low XXX following pin or signal name Memory map address Higher address on the top and lower address on the bottom Note Footnote for item marked with Note in the text Caution Information requiring particular...

Page 9: ...ister bus module 27 3 2 9 Operating clock 28 3 3 Frame Format 28 3 4 Transmission Operation 29 3 4 1 Creating transmit packet 29 3 4 2 Starting packet transmission 30 3 4 3 Setting inter packet gap 30 3 4 4 Collision and retransmission 31 3 4 5 End of or aborting transmission 31 3 5 Reception Operation 32 3 5 1 Detecting preamble and SFD 32 3 5 2 Length field check 32 3 5 3 CRC check 33 3 5 4 Pack...

Page 10: ...Port Setting Registers 65 4 3 Global Registers 94 CHAPTER 5 STATISTICS COUNTERS 99 CHAPTER 6 JTAG BOUNDARY SCAN 112 6 1 Features 112 6 2 Internal Configuration of Boundary Scan Circuit 113 6 2 1 Instruction register 113 6 2 2 TAP Test Access Port controller 113 6 2 3 Bypass register 113 6 2 4 Boundary scan register 113 6 3 Pin Function 114 6 3 1 TCK JTAG Test Clock pin 114 6 3 2 TMS JTAG Test Mode...

Page 11: ... Data Read 43 3 9 Timing for Changing Port to Be Read Using SKIP Signal Before Port Is Read 46 3 10 Timing for Changing Port to Be Read Using SKIP Signal While Port Is Read 48 3 11 Timing for Changing FIFO Bus Read Write in 64 Bit Single Bus Mode 51 3 12 Register Address Bus 53 3 13 MII Management Frame Structure 55 3 14 Connecting MII Output Signal Pins 56 3 15 Output of MII Data to Mirror Port 5...

Page 12: ... Pins and Transmit Data Attributes 64 Bit Single Bus 37 3 3 RXFDQ Pin and Receive Data Attribute 32 Bit Dual Bus 41 3 4 FDQ Pin and Receive Data Attribute 64 Bit Single Bus 42 3 5 CLKS Bit of MIIC Register and Frequency of HCLK 55 3 6 Setting of Mirror Port 0 59 3 7 Setting of Mirror Port 4 60 6 1 Operation in Each Controller State 120 ...

Page 13: ...MII and 10 Mbps serial interface as interface with physical layer devices Each port has 2K bytes of receive FIFO and 512 bytes of transmit FIFO High speed FIFO data bus interface of 32 64 bits 66 MHz Full duplex operation and IEEE 802 3x flow control Statistics counter supporting RMON SNMP Filtering conditions can be set according to address type VLAN frame detection function Mirror port function ...

Page 14: ...300 130 220 270 90 180 40 340 310 140 230 260 80 335 314 257 334 333 330 320 316 315 234 171 256 255 250 240 236 235 146 77 170 169 160 150 148 147 50 76 75 70 60 52 51 PD98431 352 PIN PLASTIC BGA TOP VIEW µ PD98431 352 PIN PLASTIC BGA BOTTOM VIEW µ Index mark Index mark AE 25 23 21 19 17 15 13 11 9 7 5 3 1 26 24 22 20 18 16 14 12 10 8 6 4 2 AC AA W U R N L J G E C A AF AD AB Y V T P M K H F D B ...

Page 15: ...RXFD8 FD8 72 E26 A6 122 AC2 RXFD5 FD5 172 B23 TXER0 23 AC1 RXFD4 FD4 73 D26 A2 123 AD2 RXFD1 FD1 173 B22 TXD02 24 AD1 RXFD0 FD0 74 C26 TDO 124 AE2 TXD43 174 B21 TXCLK0 25 AE1 TEST0 75 B26 TRST 125 AE3 TXEN4 175 B20 RXD03 26 AF1 CRS4 76 A26 TDI 126 AE4 TXD40 176 B19 RXD00 27 AF2 TXER4 77 A25 MDC 127 AE5 RXDV4 177 B18 CRS1 28 AF3 TXD42 78 A24 COL0 128 AE6 RXD41 178 B17 TXD12 29 AF4 TXCLK4 79 A23 TXE...

Page 16: ... GND 217 AD6 RXD42 255 D24 A0 293 Y4 GND 331 G23 GND 218 AD7 RXCLK4 256 C24 TMS 294 AA4 VDD 332 F23 VDD 219 AD8 TXER5 257 C23 CRS0 295 AB4 GND 333 E23 GND 220 AD9 TXD52 258 C22 TXD03 296 AC4 GND 334 D23 GND 221 AD10 RXER5 259 C21 TXD00 297 AC5 VDD 335 D22 VDD 222 AD11 TXCLK5 260 C20 RXDV0 298 AC6 CLAMP 336 D21 CLAMP 223 AD12 RXD52 261 C19 RXD01 299 AC7 GND 337 D20 GND 224 AD13 RXCLK5 262 C18 COL1 ...

Page 17: ...s interface CPU bus interface MII management interface JTAG 10 100M MAC MII 10M serial 8 MII serial management TEST port CPU BUS FIFO DATA BUS Register statistics counter 1 5 System Configuration Example Client 100M NIC CPU PHY PHY PHY PHY PHY PHY PHY PHY 100M NIC 10M NIC Giga bit backbone 1 Gbps Server GPHY GPHY SSRAM PD98421 Switch chip Multi port GMAC PD98431 µ µ ...

Page 18: ... Port 2 A 10 8 010B Port 3 A 10 8 011B Port 4 A 10 8 100B Port 5 A 10 8 101B Port 6 A 10 8 110B Port 7 A 10 8 111B D 31 0 49 50 235 51 52 148 147 53 236 149 54 237 150 55 238 151 56 239 152 57 320 240 153 58 241 154 59 242 155 60 243 244 I O 3 state Register data These pins form a bidirectional data bus through which the internal registers of the µPD98431 are accessed INT 329 O open drain Interrup...

Page 19: ...al functions as FEN If this signal goes low the FIFO bus interface is enabled and data can be read from the receive FIFO or written to the transmit FIFO TXFEN FRW 163 I FIFO bus transmission enable FIFO bus direction The function of this signal differs as follows depending on the FIFO bus mode 1 32 bit dual bus mode In this mode this signal functions as TXFEN If this signal goes low the transmit F...

Page 20: ...ort 3 TXFPT 2 0 011B Port 4 TXFPT 2 0 100B Port 5 TXFPT 2 0 101B Port 6 TXFPT 2 0 110B Port 7 TXFPT 2 0 111B TXFD 31 0 RXFD 31 0 FD 63 0 193 1 2 102 101 3 194 103 4 195 104 5 196 105 6 197 106 7 282 198 107 8 199 108 9 200 109 10 201 202 110 11 13 to 15 114 16 115 205 17 116 206 18 117 207 19 118 208 291 20 119 209 21 120 210 22 121 211 122 23 212 213 123 24 I O I O 3 state 32 bit transmit FIFO da...

Page 21: ...a on the FIFO bus in the 32 bit dual bus mode They indicate the attribute of the transmit data on FD 63 0 when the transmit FIFO is accessed for write For the input pattern of TXFDQ 3 0 refer to Table 3 1 These signals are meaningless in the 64 bit single bus mode TXFBA 7 0 156 61 245 157 62 246 159 158 O 3 state Transmit FIFO buffer available When these signals are high the transmit FIFO has spac...

Page 22: ...1 In the MII mode transmit data of nibble width 4 bits wide is output at the rising edge of TXCLK1 In the 10 Mbps serial mode only TXD1 0 is used to output serial transmit data at the rising edge of TXCLK1 TXD2 3 0 91 184 268 344 O MII transmit data port 2 These pins output transmit data to the PHY device connected to port 2 In the MII mode transmit data of nibble width 4 bits wide is output at th...

Page 23: ...7 3 0 through RXD0 3 0 that are the data received from each port and TXEN 7 0 that indicates the existence of transmit data on TXD are output in synchronization with this clock In the MII mode a 2 5 MHz clock is input for 10 Mbps operation and a 25 MHz clock is input for 100 Mbps operation In this mode RXD and RXDV are input at the rising edge of RXCLK In the 10 Mbps serial mode a 10 MHz clock is ...

Page 24: ...rom the PHY device connected to port 6 In the MII mode receive data of nibble width 4 bits wide is input at the rising edge of RXCLK6 In the 10 Mbps serial mode only RXD6 0 is used and serial receive data is input at the rising edge of RXCLK6 RXD7 3 0 231 47 144 232 I MII receive data port 7 These pins input data received from the PHY device connected to port 7 In the MII mode receive data of nibb...

Page 25: ...TMS 256 I JTAG test mode select This signal controls the boundary scan state machine This pin is internally pulled up pull up resistor 50 kΩ TDI 76 I JTAG test data input This signal is serial data input for boundary scan This pin is internally pulled up pull up resistor 50 kΩ TDO 74 O 3 state JTAG test data output This signal is serial data output for boundary scan TCK 169 I JTAG test clock This ...

Page 26: ...1 314 317 321 323 326 328 332 335 338 341 345 346 349 352 Power supply 3 3 V GND 277 278 280 281 284 286 287 289 292 293 295 296 299 302 305 309 312 315 316 318 319 322 324 325 327 330 331 333 334 337 340 343 347 350 Ground 0 V CLAMP 298 301 304 310 313 336 339 342 348 351 Clamp power supply This pin supplies a clamp voltage to the MII buffer circuit Supply 5 V to this pin when an external 5 V PHY...

Page 27: ...ith an external 10 Mbps transceiver which transmits clocked serial data can be realized Half duplex or full duplex operation can be performed by all the ports of the µPD98431 and in each network interface mode Two system interfaces FIFO bus interface and register bus interface are available The FIFO bus interface connects an upper layer with the internal FIFOs of the µPD98431 This interface has a ...

Page 28: ...64 bit single bus CPU bus Test port MII management 3 2 1 MAC module The MAC module realizes a 10 100M Ethernet MAC function and is designed to connect a PHY device supporting MII If a PCS module is connected to the MAC module the µPD98431 can be connected to a 10BASE T transceiver having a 10 Mbps serial interface The MAC module has a transmission block reception block and MAC control block The tr...

Page 29: ...ess whether the broadcast packet is received or not can be selected In addition the µPD98431 can also accept all packets for all address types For address filtering conditions refer to 3 5 5 Address filtering 3 2 4 STAT STATistics counter module The µPD98431 has a statistics counter set that is useful for implementing RMON SMNP for each port The STAT module implements this statistics counter set F...

Page 30: ...FIFOs of the µPD98431 or read from the FIFOs to the host system in synchronization with this FCLK signal The frequency of the FLCK signal is in the range 66 to 25 MHz 3 3 Frame Format In an Ethernet network information is transmitted or received in the form of a packet or frame The frame format used for Ethernet consists of preamble PA start frame delimiter SFD destination address DA source addres...

Page 31: ...the host system to the transmit FIFO includes a destination address and the last valid data in the data field The preamble SFD and FCS necessary for a transmit packet frame can be automatically appended by the µPD98431 1 Appending preamble and SFD The µPD98431 always appends a preamble and SFD to the transmit data in the transmit FIFO and outputs the data to the network 2 Appending CRC The µPD9843...

Page 32: ...other station is transmitting data and if the gap between packets that was determined in advance when the previous data transmission was completed or inter packet gap is satisfied outputting a transmit data stream to the PHY device is immediately started If any other station is transmitting data the µPD98431 waits until the communication ends and postpones its transmission until the inter packet g...

Page 33: ...n which the condition occurs is cleared and the other transmit packet data already accumulated is not affected The occurrence of this condition causes the INT signal to go low If the number of collisions exceeds the maximum number of times the ECOL bit of the TSVERG1 register is set to 1 If a collision occurs after the collision window period the LCOL bit of the TSVREG1 register is set to 1 The in...

Page 34: ...receive data to the host system from the receive data stream sent from the PHY device It detects the preamble and SFD checks the length field and executes CRC check Status information on each received packet such as the number of received bytes and occurrence of errors is written to the RSVREG register after reception has been completed This status information can be appended to the data stream ou...

Page 35: ...1 and HT2 registers A filtering condition can be also set for each address type of unicast address multicast address and broadcast address In addition two or more of the filtering conditions described below can be used in combination 1 Filtering of unicast address The station address set by the LSA1 and LSA2 registers is used as a unicast address and is compared with the destination address of the...

Page 36: ...le receive packets are being stored in the receive FIFO the packet being received is discarded If the preceding receive packet has been already stored in the receive FIFO at this time this packet is also cleared 3 6 Full Duplex Operation Each port of the µPD98431 can execute full duplex operation and can transmit and receive packets simultaneously If the FULLD bit of the MACC1 register is set to 1...

Page 37: ... 31 0 Idle Start Middle 3 byte ending Idle Port N 1st word 32 bits 2nd word 32 bits 3rd word 32 bits 4th word 32 bits n 2 th word 32 bits n 1 th word 32 bits n th word 24 bits b Example in 64 bit single bus mode FCLK FEN FRW TXFBA N FDQ 3 FDQ 2 FDQ 1 FDQ 0 TXFPT 2 0 FD 63 0 Port N 1st word 64 bits 2nd word 64 bits 3rd word 64 bits 4th word 64 bits n 2 th word 64 bits n 1 th word 64 bits n th word ...

Page 38: ...it FIFO to which it will write data to these pins TXFD 31 0 and FD 63 0 are the data buses through which data is written to the transmit FIFO in the respective bus modes TXFDQ 3 0 and FDQ 3 0 are signals indicating the attribute of the data on the FIFO data bus and input the attribute of the data on TXFD 31 0 or FD 64 0 in each bus mode of the host system The attributes of data include idle data s...

Page 39: ...fer If the quantity of the data in the transmit FIFO exceeds the value set to the TFDWH field of the TFIC register the TXFBAn signal goes low By specifying idle in the middle of burst transfer writing to the transmit FIFO can be postponed By changing TXFPT 2 0 while data is written to the transmit FIFO the transmit data can be written to the transmit FIFO of another port In this case the data can ...

Page 40: ...32 bits 2nd word 32 bits 3rd word 32 bits 4th word 32 bits 1st word 32 bits 2nd word 32 bits 3rd word 32 bits Port N Middle Port N Port M 4th word 32 bits 5th word 32 bits b Example in 64 bit single bus mode FCLK FEN FRW TXFBA M TXFBA N FDQ 3 FDQ 2 FDQ 1 FDQ 0 TXFPT 2 0 FD 63 0 Port M 1st word 64 bits 2nd word 64 bits 3rd word 64 bits 4th word 64 bits 1st word 64 bits 2nd word 64 bits 3rd word 64 ...

Page 41: ...red until attribute data indicating the end of the data EOF is provided to the TXFDQ or FDQ pin The host system can write the next packet after inputting EOF If a cause that aborts transmission occurs in the transmit packet that has been already accumulated in the transmit FIFO and is waiting to be transmitted while data is written to the transmit FIFO transmission of that packet is canceled and t...

Page 42: ...K RXFEN RXFA RXFDQ 3 RXFDQ 2 RXFDQ 1 RXFDQ 0 RXFPT 2 0 RXFD 31 0 PASS SKIP Idle Start Middle 3 byte ending Idle 1st Dword 32 bits 2nd Dword n th Dword n 1 th Dword Port N b Example in 64 bit single bus mode FCLK RXFEN FRW RXFA FDQ 3 FDQ 2 FDQ 1 FDQ 0 RXFPT 2 0 FD 63 0 PASS SKIP Idle Start Middle 7 byte ending Idle 1st Dword 64 bits 2nd 64 bits n th 64 bits n 1 th 64 bits Port N ...

Page 43: ...receive FIFO that is ready for data transfer to RXFPT 2 0 After the host system recognizes RXFPT 2 0 it must input the PASS signal to read data from the receive FIFO of the port When the PASS signal is input the receive data can be read from RXFD 31 0 or FD 63 0 in the burst format as a receive data stream synchronized with FCLK As soon as the receive data has been read the µPD98431 outputs the da...

Page 44: ...dian refer to 3 7 1 4 Little endian big endian When reading of the one packet specified by RXFPT has been completed the µPD98431 then makes the RXFA signal high if any of the ports is ready for reading receive data outputs the port number to RXFPT and waits for reading the next receive data The RXFA signal remains high if receive data ready to be read exists in the port indicated by RXFPT However ...

Page 45: ... Port After Completion of Received Data Read 1 2 a Example in 32 bit dual bus mode FCLK RXFEN RXFA RXFDQ 3 RXFDQ 2 RXFDQ 1 RXFDQ 0 RXFPT 2 0 RXFD 31 0 PASS SKIP Port N Port M Start Middle Middle 3 byte ending 1st Dword 2nd Dword 3rd Dword n th 24 bits n 1 th Dword n 2 th Dword n 3 th Dword Idle ...

Page 46: ...ng a CRC error control frame or short packet is not received these packets are stored briefly in the receive FIFO However the contents of the receive FIFO are cleared when the CRC error is confirmed and the µPD98431 does not inform the host system that it stored the packets The same applies to address filtering A packet that does not satisfy the filtering condition is deleted from the receive FIFO...

Page 47: ...ce Next it outputs the port number of the next port that is ready for transferring receive data to the RXFPT and makes the RXFA signal high again If the PASS signal is input from the host system at this time data is read from the next port The data of the port that is skipped by the SKIP signal is retained If reading the receive data of the other port has been completed or if the original port is ...

Page 48: ... bit dual bus mode FCLK RXFEN RXFA RXFDQ 3 RXFDQ 2 RXFDQ 1 RXFDQ 0 RXFPT 2 0 RXFD 31 0 PASS SKIP Port N Port M Skip frame Start Middle Idle XX XX 1st Dword 1st Dword 2nd Dword b Example in 64 bit single bus mode Skip frame Start Middle Idle FCLK FEN FRW RXFA FDQ 3 FDQ 2 FDQ 1 FDQ 0 RXFPT 2 0 FD 31 0 PASS SKIP Port N Port M XX XX 1st 64 bits 1st 64 bits 2nd 64 bits ...

Page 49: ... the PASS signal is necessary for starting to read If the port that has been skipped by the SKIP signal is selected again the port starts outputting receive data next to the one that was output last when the port was skipped By using the SKIP signal therefore the data received by each port can be divided into blocks and read Determine a unit in which data is to be divided and read and input the SK...

Page 50: ...N RXFA RXFDQ 3 RXFDQ 2 RXFDQ 1 RXFDQ 0 RXFPT 2 0 RXFD 31 0 PASS SKIP Port M Port N 1st Dword 32 bits 1st Dword 32 bits 2nd Dword n th Dword n 1 th Dword n 3 th Dword n 2 th Dword b Example in 32 bit dual bus mode if the next port is the port skipped FCLK RXFEN RXFA RXFDQ 3 RXFDQ 2 RXFDQ 1 RXFDQ 0 RXFPT 2 0 RXFD 31 0 PASS SKIP Port N Port N XX XX 1st Dword 32 bits 2nd Dword n th Dword n 1 th Dword ...

Page 51: ...Q 0 RXFPT 2 0 RXFD 63 0 PASS SKIP Port M Port N 1st word 64 bits 1st word 64 bits n th word 64 bits n 1 th word 64 bits n 2 th word 64 bits n 3 th word 64 bits 2nd word 64 bits d Example in 64 bit single bus mode if the next port is the port skipped FCLK FEN FRW RXFA FDQ 3 FDQ 2 FDQ 1 FDQ 0 RXFPT 2 0 FD 63 0 PASS SKIP Port N Port N XX XX 1st word 64 bits n 1th word 64 bits n th word 64 bits n 1 th...

Page 52: ...riting transmit data in the 64 bit single bus mode Be sure to deassert the FEN signal once before switching the operation from reading to writing or vice versa If the FEN signal is deasserted during a write operation detection of deasserting the FEN signal to the next rising edge of FCLK is assumed as valid writing If the FEN signal is deasserted during a read operation the valid data is output af...

Page 53: ... 2 a Example of timing for changing write cycle to read cycle FCLK FEN FRW TXFBA N RXFA FDQ 3 FDQ 2 FDQ 1 FDQ 0 RXFPT 2 0 TXFPT 2 0 FD 63 0 PASS SKIP Idle Start Middle Middle TA Port N Port N Port N 3 byte ending 1st word 64 bits n th word 64 bits n 1 th word 64 bits n 2 th word 64 bits n 4 th word 64 bits n 3 th word 64 bits 2nd word 64 bits ...

Page 54: ...or big endian as the byte order of the transmit receive data on the FIFO interface Little endian or big endian is selected by using the BUSMODE bit of the MACC3 register In the little endian mode data is transferred starting from the least significant byte of the data bus In the big endian mode data transfer starts from the most significant byte The setting of the BUSMODE bit of the MACC3 register...

Page 55: ...gnal low to report to the host system The host system must keep the statuses of the A 10 0 D 31 0 RW and CS signals until the ACK signal goes low and the host system has completed writing data When writing has been completed and the host system makes the CS signal high the µPD98431 completes the write cycle The ACK signal goes low for the duration of one cycle of HCLK 2 Register address mapping Th...

Page 56: ... to 1 Each status register is automatically cleared when it is read while the SRRC bit of the MISCR register is set to 1 The INT signal is deasserted when the status registers of all the ports except the masked bits have been cleared 3 8 Network Interface The µPD98431 has an MII Media Independent Interface and a 10 Mbps serial interface to interface the network The interface to be used can be sele...

Page 57: ... the MWTD register The µPD98431 first outputs serial data from the preamble to REGAD as an MDIO signal and after turn around outputs the data set to the CLTD field of the MWTD register for write access For read access serial data is input from the MDIO signal and is written to the PRSD field of the MRDD register 3 Access procedure The MII management frame is transmitted or received as follows Firs...

Page 58: ...g the pause control frame defined by IEEE802 3x Annex31B The purpose of flow control is to lower the frequency at which packets are transmitted from the other terminals connected to the µPD98431 on a point to point basis for full duplex operation When a pause control frame is received the value of the pause timer field in the control frame is loaded to the pause timer in the MAC If the pause timer...

Page 59: ...e length type field and a pause op code of 0001H is appended to the control op code field In addition the value set to the PTIME field of the MACC3 register is appended as the value of the pause timer After the quantity of data in the receive FIFO has exceeded the threshold value of the RFDMH field and the µPD98431 has automatically transmitted the pause control frame the data stored in the receiv...

Page 60: ...cs counter set that is useful for implementing RMON and SNMP for each port The statistics counter is a 32 bit counter and supplies the upper layer with a total of 41 pieces of information on transmission and reception The statistics counter counts and retains statistical parameters related to transmission reception of packets for details of the parameters counted refer to CHAPTER 5 STATISTICS COUN...

Page 61: ...nd P4EN bit of the MIRR register to 1 respectively When the P0EN or P4EN bit is set to 1 the MII data stream of a port selected by the MP0 1 0 or MP4 1 0 field of the MIRR register is output to the corresponding mirror port as a transmit MII data stream Whether the mirrored data stream is transmit data or receive data is selected by using the T R0 or T R4 bit of the MIRR register Tables 3 6 and 3 ...

Page 62: ...n Because the register setting before the port enters the sleep status is not held the registers must be re set after the port has been released from the sleep status Because HCLK is not supplied to a sleeping port the setting register of the port cannot be accessed while the port is sleeping Because the register setting before the port enters sleep status is not preserved it must be set again aft...

Page 63: ...TIME pause frame is transmitted once by regarding only the last condition as valid Depending on the interval at which the condition occurs however the PTIME pause frame is transmitted two times The 0 pause frame is transmitted if the quantity of the data in the receive FIFO falls below the value of RFDML of the RFIC1a register after the condition for transmitting the PTIME pause frame has been sat...

Page 64: ...at all the ports are initialized 4 Cautions on switching settings of MACC1 MACC2 MACC3 PCSC registers Observe the following points when switching the settings of the MACC1 MACC2 MACC3 and PCSC registers With the exception of the SRXEN bit of the MACC1 register the PTIME bit of the MACC3 register and all the software reset bits when switching the settings of the bits in the MACC1 MACC2 MACC3 and PC...

Page 65: ...ion address register 2 R W 00000000H 17H PTVR Pause timer value read register R 00000000H 18H Reserved 19H VLTP VLAN type register R W 00000000H 1AH to 1FH Reserved 20H MIIC MII configuration register R W 00000000H 21H to 24H Reserved 25H MCMD MII command register W 00000000H 26H MADR MII address register R W 00000000H 27H MWTD MII write data register R W 00000000H 28H MRDD MII read data register ...

Page 66: ...nsmit status register 2 R 00000000H 95H RSVREG Receive status register R 00000000H 96H FSVREG FIFO status register R 00000000H 97H Reserved 98H PCSC PCS configuration register R W 00000000H 99H to 9AH Reserved 9BH RFIC1 Receive FIFO configuration register 1 R W 07FF0000H 9CH RFIC2 Receive FIFO configuration register 2 R W 07FF0007H 9DH TFIC Transmit FIFO configuration register R W 00FF00FFH 9EH to...

Page 67: ...10 RXFC Reception flow control enable When this bit is set to 1 the pause operation is executed for the duration of the pause time set by the pause timer The value of the pause timer is updated when a valid pause control frame is received regardless of the setting of this bit 0 9 SRXEN Reception enable If this bit is set to 1 writing receive packet data from the network to the receive FIFO is enab...

Page 68: ... set to 1 the full duplex operation is performed 0 0 HUGEN Large packet enable When this bit is cleared to 0 transmission or reception of a packet exceeding the value of the LMAX register is aborted Caution If this bit is 1 the constraint of the LMAX register is cleared If a packet is received exceeding the upper limit of the receive FIFO set by RFUB of the RFIC2 register a receive FIFO overrun oc...

Page 69: ...bit is set to 1 a transmit packet regarded as a VLAN packet is processed based on MAX 1522 bytes MIN 64 bytes However if this bit is 1 and if the PADEN bit of the MACC1 register is also 1 pad and CRC are automatically appended to the transmit packets regarded as VLAN packets that are less than 68 bytes and packets are transmitted as 68 bytes The µPD98431 regards the transmit packets matching the V...

Page 70: ... address A 7 0 03H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IPGR1 Reserved IPGR2 Bit Name Function Default 31 15 Reserved Write 0 to these bits 14 8 IPGR1 Carrier sense period This field sets the carrier sense period of the first half of a non back to back IPG by using the following expression Carrier sense period 2 IPGR1 4 bits ti...

Page 71: ...llision occurs If retransmission is not completed within the value set by this field transmission is aborted This value indicates the maximum number of times of collision 0FH LMAX Maximum packet length register register address A 7 0 05H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAXF 15 0 Bit Name Function Default 31 16 Reserved Write 0 to t...

Page 72: ...sed 0 LSA2 Station address register 2 register address A 7 0 16H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SA 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SA 15 0 Bit Name Function Default 31 0 LSA2 Station address SA 31 0 0 PTVR Pause timer value read register register address A 7 0 17H Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 73: ... frame as a VLAN frame 0 MIIC MII configuration register register address A 7 0 20H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIRST Reserved CLKS Reserved Bit Name Function Default 31 16 Reserved Write 0 to these bits 15 MIRST MII management interface block software reset When this bit is set to 1 the MII management interface block is reset ...

Page 74: ... 0 Caution When accessing this register input 000B to A 10 8 MADR MII address register register address A 7 0 26H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIAD 4 0 Reserved RGAD 4 0 Bit Name Function Default 31 13 Reserved Write 0 to these bits 12 8 FIAD MII PHY address This field sets a PHY address to select one of the 32 PHY devi...

Page 75: ...ly 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRSD 15 0 Bit Name Function Default 31 16 Reserved 15 0 PRSD MII read data This is a read data field used for read access by the MII management interface 0 Caution When accessing this register input 000B to A 10 8 MIND MII indicator register register address A 7 0 29H Read only 31 30 29 28 27 26 25 24...

Page 76: ...coincides with a hash table is accepted 0 0 ABC Broadcast reception In this mode broadcast packets are accepted 0 HT1 Hash table register 1 register address A 7 0 33H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HT 63 48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HT 47 32 Bit Name Function Default 31 0 HT1 Hash table 1 This table is used for conditional multicast packet detection These bits are ...

Page 77: ...nter refer to CHAPTER 5 STATISTICS COUNTERS If this register is read when the SRRC bit of the MISCR register is set to 1 all the bits are automatically cleared Bit Name Function Default 31 16 Reserved Write 0 to these bits 15 C1VT RVBT counter carry bit 0 14 C1UT TUCA counter carry bit 0 13 C1BT TBCA counter carry bit 0 12 C1MT TMCA counter carry bit 0 11 C1PT TPKT counter carry bit 0 10 C1TB TBYT...

Page 78: ...lly cleared Bit Name Function Default 31 C2DV Status vector overrun This bit indicates that a status FIFO overrun in the statistics counter 0 30 23 Reserved Write 0 to these bits 22 C2IM TIME counter carry bit 0 21 C2CS TCSE counter carry bit 0 20 C2NC TNCL counter carry bit 0 19 C2XC TXCL counter carry bit 0 18 C2LC TLCL counter carry bit 0 17 C2MC TMCL counter carry bit 0 16 C2SC TSCL counter ca...

Page 79: ...ch bit of the CAR1 register can be masked Bit Name Function Default 31 16 Reserved Write 0 to these bits 15 M1VT RVBT counter carry mask bit 0 14 M1UT TUCA counter carry mask bit 0 13 M1BT TBCA counter carry mask bit 0 12 M1MT TMCA counter carry mask bit 0 11 M1PT TPKT counter carry mask bit 0 10 M1TB TBYT counter carry mask bit 0 9 M1MX RMAX counter carry mask bit 0 8 M11K R1K counter carry mask ...

Page 80: ... bit 0 19 M2XC TXCL counter carry mask bit 0 18 M2LC TLCL counter carry mask bit 0 17 M2MC TMCL counter carry mask bit 0 16 M2SC TSCL counter carry mask bit 0 15 M2XD TXDF counter carry mask bit 0 14 M2DF TDFR counter carry mask bit 0 13 M2XF TXRF counter carry mask bit 0 12 M2TE TFCS counter carry mask bit 0 11 M2JB RJBR counter carry mask bit 0 10 M2FG RFRG counter carry mask bit 0 9 M2OV ROVR c...

Page 81: ...is prefixed to the receive data stream read from the FIFO bus Caution Do not set the APSE and APSS bits to 1 at the same time 0 4 BUSMODE Little endian big endian When this bit is 1 the byte order of the FIFO bus is big endian 0 3 BACKPE Back pressure enable When this bit is 1 the back pressure function is enabled 0 2 FLWCNT Transmission flow control enable When this bit is 1 automatic transmissio...

Page 82: ...rier sense error When this bit is 0 the interrupt of the corresponding bit of the TSVREG1 register is masked 0 14 ITBR Back pressure When this bit is 0 the interrupt of the corresponding bit of the TSVREG1 register is masked 0 13 ITPP Transmission request during pause When this bit is 0 the interrupt of the corresponding bit of the TSVREG1 register is masked 0 12 ITPCF Pause control frame transmis...

Page 83: ...n this bit is 0 the interrupt of the corresponding bit of the TSVREG1 register is masked 0 3 ITDONE End of transmission When this bit is 0 the interrupt of the corresponding bit of the TSVREG1 register is masked 0 2 ITFLOR Length field check When this bit is 0 the interrupt of the corresponding bit of the TSVREG1 register is masked 0 1 ITFLER Data length non coincidence When this bit is 0 the inte...

Page 84: ...eive packet length error When this bit is 0 the interrupt of the corresponding bit of the RSVREG register is masked 0 14 IVLAN VLAN frame When this bit is 0 the interrupt of the corresponding bit of the RSVREG register is masked 0 13 IUSOP Reception of control frame including undefined op code When this bit is 0 the interrupt of the corresponding bit of the RSVREG register is masked 0 12 IRPCF Pau...

Page 85: ...bit is 0 the interrupt of the corresponding bit of the RSVREG register is masked 0 3 IRCV RXER detection When this bit is 0 the interrupt of the corresponding bit of the RSVREG register is masked 0 2 ICEPS False Carrier detection When this bit is 0 the interrupt of the corresponding bit of the RSVREG register is masked 0 1 IREPS Invalid packet reception When this bit is 0 the interrupt of the corr...

Page 86: ... CSE Carrier sense error When this bit is 1 it indicates that a carrier sense error has occurred during transmission 0 14 TBP Back pressure When this bit is 1 it indicates that a dummy packet has been transmitted by backpressure and that a collision has occurred 0 13 ITPP Transmission request during pause When this bit is 1 it indicates that transmission of the packet requested has been completed ...

Page 87: ...d 0 3 TDONE End of transmission When this bit is 1 it indicates that transmission has been completed normally This bit is not set to 1 if transmission is aborted 0 2 TFLOR Length field check When this bit is 1 it indicates that the value of the length field of the transmit packet exceeds 1500 This bit is not set to 1 if the FLCHT bit of the MACC1 register is 0 0 1 TFLER Data length non coincidence...

Page 88: ...ion or when transmission is aborted If this register is read when the SRRC bit of the MISCR register is set to 1 all the bits are automatically cleared Bit Name Function Default 31 16 TTBC Total transmit byte count This field indicates the total number of bytes including packets canceled because of occurrence of a collision that have been transmitted before transmission is completed 0 15 0 TBYT Tr...

Page 89: ...greater than 1518 octet less than 64 octet or greater than 1522 octet in the case of VLAN 0 14 VLAN VLAN frame When this bit is 1 it indicates that the VPID field of the received packet coincides with the value of the VLTP register This bit is not set to 1 if a CRC error or RXER occurs 0 13 USOP Reception of control frame including undefined op code When this bit is 1 it indicates that a control f...

Page 90: ... RXER detection When this bit is 1 it indicates that RXER has been detected 0 2 CEPS False Carrier detection When this bit is 1 it indicates that False Carrier has been detected after the preceding reception 0 1 REPS Invalid packet reception When this bit is 1 it indicates that an invalid packet only preamble SFD or packet with only 1 nibble of data has been received after the preceding reception ...

Page 91: ...nction Default 31 11 Reserved 10 TFOV Transmit FIFO overrun This bit is set to 1 if an overrun occurs in the transmit FIFO 0 9 TFUN Transmit FIFO underrun This bit is set to 1 if an underrun occurs in the transmit FIFO 0 8 TWMH Transmission full level over This bit is set to 1 if the quantity of data in the transmit FIFO exceeds the value set by the TFDMH field of the TFIC register 0 7 3 Reserved ...

Page 92: ...back When this bit is set to 1 the PCS transmit data output is looped back as PCS receive data input 0 1 EXINT Physical layer interface selection This bit selects an interface with the physical layer device When this bit is cleared to 0 the MII mode is selected when it is set to 1 the 10 Mbps serial mode is selected 0 0 ENJAB Jabber protection enable When this bit is set to 1 the jabber packet is ...

Page 93: ...rol function is enabled and if the quantity of data in the receive FIFO has once exceeded the value set to the RFDMH field and then falls below the value of this field a control frame with a pause timer value of 0 is automatically transmitted Caution The relation between the set value of RFDMH and that of RFDML must be as follows 0 RFDML RFDMH 7FFH 000H Caution In the FIFO of the µ µ µ µPD98431 th...

Page 94: ...d An undefined control frame other than the pause frame is not discarded 1 Notes 1 In the FIFO of the µPD98431 the packet data quantity is used in 4 byte units in the 32 bit bus mode and in 8 byte units in the 64 bit bus mode If a fraction occurs at the end of a packet the value rounded up in data units of each bus mode is regarded as the quantity of the accumulated data in the FIFO To compare the...

Page 95: ...f this field the TXFBA n signal is made low Set a value to this field in the range 3FH to 1FFH 0FFH 15 9 Reserved Write 0 to these bits 0 8 0 TFDWL Transmission drain level If the quantity of data in the transmit FIFO has exceeded the value of this field transmission of a packet is started Set a value to this field in the range the value of CLRT register LCOL 8 to 1FFH 0FFH Caution In the FIFO of ...

Page 96: ...1 if any bit of the TSVREG1 register of port 7 is set to 1 0 30 P7RS Port 7 RSVREG status This bit is set to 1 if any bit of the RSVREG register of port 7 is set to 1 0 29 P7FS Port 7 FSVREG status This bit is set to 1 if any bit of the FSVREG register of port 7 is set to 1 0 28 P7CA Port 7 CAR status This bit is set to 1 if any bit of the CAR1 or CAR2 register of port 7 is set to 1 0 27 P7TS Port...

Page 97: ...e TSVREG1 register of port 2 is set to 1 0 10 P7RS Port 2 RSVREG status This bit is set to 1 if any bit of the RSVREG register of port 2 is set to 1 0 9 P7FS Port 2 FSVREG status This bit is set to 1 if any bit of the FSVREG register of port 2 is set to 1 0 8 P7CA Port 2 CAR status This bit is set to 1 if any bit of the CAR1 or CAR2 register of port 2 is set to 1 0 7 P7TS Port 1 TSVREG status This...

Page 98: ...0 to these bits 16 BUSWTH FIFO bus interface data bus width When this bit is 0 the data bus width of the FIFO bus interface is 32 bits 32 bit dual bus mode When it is 1 the data bus width of the FIFO bus interface is 64 bits 64 bit single bus mode 0 15 9 Reserved Write 0 to these bits 8 INTEN Interrupt enable When this bit is 1 the function of the INT signal is enabled 0 7 1 Reserved Write 0 to th...

Page 99: ... a port mirrored by port 4 The relation between the bits of this field and ports is as follows MP4 1 0 11B Port 7 MP4 1 0 10B Port 6 MP4 1 0 01B Port 5 MP4 1 0 00B Port 4 0 4 MP4EN Port 4 mirroring enable When this bit is 1 port mirroring by port 4 is enabled 0 3 TR0 Transmission reception selection mirror port port 0 When port 0 is used as a mirror port this bit selects whether transmission or re...

Page 100: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved POWD Bit Name Function Default 31 8 Reserved Write 0 to these bits 7 0 POWD Setting of power down mode This field sets a power down mode By setting a bit of this field to 1 clock supply to the corresponding port in the device is cut Bits 7 through 0 correspond to ports 7 through 0 respectively 0 ...

Page 101: ...eption counter R W 00000000H 5EH RFRG Error short packet reception counter R W 00000000H 5FH RJBR Error jabber packet reception counter R W 00000000H 60H R64 64 byte frame reception counter R W 00000000H 61H R127 65 to 127 byte frame reception counter W 00000000H 62H R255 128 to 255 byte frame reception counter R W 00000000H 63H R511 256 to 511 byte frame reception counter R W 00000000H 64H R1K 51...

Page 102: ...lti collision packet transmission counter R W 00000000H 7BH TLCL Late collision counter R W 00000000H 7CH TXCL Excessive collision counter R W 00000000H 7DH TNCL Total collision counter R W 00000000H 7EH TCSE Carrier sense error counter R W 00000000H 7FH TIME MAC internal error counter R W 00000000H 80H RFOVR Receive FIFO overrun counter R W 00000000H 81H TFUNR Transmit FIFO underrun counter R W 0...

Page 103: ... counter register address A 7 0 51H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PRKT 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRKT 15 0 This counter counts all the receive packets including packets in which an error has occurred all the unicast packets all the multicast packets and all the broadcast packets RFCS CRC error reception counter register address A 7 0 52H R W 31 30 29 28 27 2...

Page 104: ... 6 5 4 3 2 1 0 RBCA 15 0 This counter counts broadcast packets with a length of longer than 64 bytes and less than 1518 bytes less than 1522 bytes in the case of a VLAN frame when such packets have been received Multicast packets are not included Note also that receive packets in which a CRC error occurred are not counted RXCF Control frame reception counter register address A 7 0 55H R W 31 30 29...

Page 105: ... is received when the HUGEN bit of the MACC1 register is 0 an alignment error check is performed as soon as the set value byte unit of the LMAX register is reached so this counter is not incremented RFLR Data length non coincidence reception counter register address A 7 0 59H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RFLR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFLR 15 0 This counter...

Page 106: ...the receive packet is less than 64 bytes long and includes a valid FCS field ROVR Jabber packet reception counter register address A 7 0 5DH R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ROVR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ROVR 15 0 This counter is incremented if the receive packet is longer than 1518 bytes less than 1522 bytes in the case of a VLAN frame and includes a valid FC...

Page 107: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R64 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R64 15 0 This counter is incremented if the receive packet length is 64 bytes Packets including a CRC error symbol error or length type error are also counted R127 65 to 127 byte frame reception counter register address A 7 0 61H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R127 31 16 15 14 13 1...

Page 108: ...ted if the receive packet length is 512 to 1023 bytes Packets including a CRC error symbol error or length type error are also counted RMAX 1024 to RMAX byte frame reception counter register address A 7 0 65H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RMAX 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMAX 15 0 This counter is incremented if the receive packet length is 1024 to 1518 bytes 1...

Page 109: ... a packet has been transmitted including a packet in which an error has occurred all unicast packets all multicast packets and broadcast packets TFCS CRC error transmission counter register address A 7 0 72H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TFCS 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TFCS 15 0 This counter is incremented if a CRC error is detected in the FCS field that has ...

Page 110: ...been transmitted This counter is not incremented if transmission is aborted or if a CRC error has been detected TXPF Pause control frame transmission counter register address A 7 0 76H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXPF 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXPF 15 0 This counter is incremented by the pause control frame automatic transmission function of the µPD98431 e...

Page 111: ... is incremented if transmission is successful after a collision has occurred once during transmission TMCL Multi collision packet transmission counter register address A 7 0 7AH R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMCL 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMCL 15 0 This counter is incremented if transmission is successful after multiple collisions at least two and no more th...

Page 112: ... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TNCL 15 0 This counter counts the total number of collisions after which transmission is successful TCSE Carrier sense error counter register address A 7 0 7EH R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TCSE 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCSE 15 0 This counter is incremented if a carrier sense error occurs during transmission TIME MAC i...

Page 113: ...ounter does not have a carry bit If it overflows this counter is cleared to 0 in the same manner as the other statistics counters TFUNR Transmit FIFO underrun counter register address A 7 0 81H R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TFUNR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TFUNR 15 0 This counter is incremented if the transmit FIFO underruns Caution This counter does not have...

Page 114: ...n Standard Three registers dedicated to boundary scan Instruction register Bypass register Boundary scan register Two instructions supported BYPASS instruction EXTEST instruction SAMPLE PRELOAD instruction Five pins dedicated to boundary scan 5 pins TCK JTAG Test Clock TMS JTAG Test Mode Select TDI JTAG Test Data Input TDO JTAG Test Data Output TRST JTAG Reset ...

Page 115: ...at the rising edge of the clock input to the TCK pin 6 2 3 Bypass register The bypass register consists of a 1 bit shift register connected between the TDI and TDO pins when the TAP controller is in Shift DR state If this register is selected while the TAP controller is in Shift DR state data is shifted to the TDO pin at the rising edge of the clock input to the TCK pin When this register is selec...

Page 116: ...nput to the TCK pin and defines the operation of the TAP controller 6 3 3 TDI JTAG Test Data Input pin The TDI pin is an input pin that inputs data to the JTAG boundary scan circuit register 6 3 4 TDO JTAG Test Data Output pin The TDO pin is an output pin that outputs data from the JTAG boundary scan circuit This pin changes its output at the falling edge of the clock input to the TCK pin This pin...

Page 117: ...e instruction register boundary scan register and bypass register change at the rising or falling edge of the clock input to the TCK pin Refer to Figure 6 3 Figure 6 2 State Transition of TAP Controller H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L 1 Test Logic Reset 2 Run Test Idle 3 Select DR Scan 4 Select IR Scan 5 Capture DR 11 Capture IR 6 Shift DR 12 Shift IR 7 Exit1 DR 13 ...

Page 118: ...ts from the Test Logic Reset state the controller enters the Run Test Idle state In this state no operation is performed because the current instruction is set by the operation of the bypass register The logic operation of the JTAG boundary scan circuit is inactive even in the Select DR Scan and Select IR Scan states 2 Run Test Idle The TAP controller is in this state during scan operation in Sele...

Page 119: ...oward the serial output direction at each rising edge of the TCK pin signal The boundary scan register or bypass register selected by the current instruction holds the previous status without change if the controller is not on the serial bus not in the Shift DR state While the controller is in this state the instruction does not change If the TAP controller is in this state at the rising edge of t...

Page 120: ...held high at the rising edge of the TCK pin signal with the TAP controller in this state the controller enters the Select DR Scan state If the TMS pin signal is held low at the rising edge of the TCK signal the TAP controller enters the Run Test Idle state 11 Capture IR In this controller state the shift register loads the pattern of a fixed logic value 01 binary to the instruction register at the...

Page 121: ...pin signal is held high at the rising edge of the TCK pin signal the TAP controller enters the Update IR state This ends the scan process If the TMS pin signal is held low at the rising edge of the TCK pin the TAP controller enters the Shift IR state Both the bypass register and boundary scan register selected by the current instruction retain their states without change While the TAP controller i...

Page 122: ...peripheral circuit that selects a register whose contents are to be output to the TDO pin are controlled as shown in Table 6 1 The TDO pin defined in this table changes at the falling edge of the TCK pin signal after it has entered each state Table 6 1 Operation in Each Controller State Controller State Selected Register to Be Driven to TDO Pin TDO Pin Driver Test Logic Reset Undefined High impeda...

Page 123: ...Exit2 IR Pause IR Bypass New instruction Old data Instruction register Inactive Active Inactive Active Inactive TCK pin signal TMS pin signal Controller state TDI pin signal Input data to IR IR shift register Parallel output of IR Input data to TDRNote TDR shift register Parallel output of TDR Selected register TDO enable signal TDO pin signal Note TDR Test Data Register Boundary scan register and...

Page 124: ...pdate DR Exit2 DR Pause DR TCK pin signal TMS pin signal Controller state TDI pin signal Input data to IR IR shift register Parallel output of IR Input data to TDRNote TDR shift register Parallel output of TDR Selected register TDO enable signal TDO pin signal Bypass Instruction Inactive Active Inactive Old data New instruction Inactive Active Note TDR Test Data Register Boundary scan register and...

Page 125: ...nd Test Logic Reset controller states 2 Data is not inverted since it has been serially input to the instruction register until it is serially output 3 A fixed binary pattern data 01 with LSB Least Significant Bit being 1 is loaded to this register cell in the Capture IR controller state 4 A fixed binary pattern data 01 with LSB being 1 is loaded to this register cell in the Test Logic Reset contr...

Page 126: ...hift DR controller state this instruction is used to select the boundary scan register of serial access between the TDI and TDO instructions While this instruction is selected The states of all the signals driven from the system output pins are completely defined by the data shifted to the boundary scan register In the Update DR controller state the states of all the signals are changed only by th...

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