7542 Group
Rev.3.02 Oct 31, 2006 Page 31 of 134
REJ03B0006-0302
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P1
4
/CNTR
0
pin is measured.
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR
0
pin.
When the CNTR
0
active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR
0
pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR
0
active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR
0
pin is “L”. The count
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
■
Note on Timer X
(1) CNTR
0
interrupt active edge selection-1
CNTR
0
interrupt active edge depends on the CNTR
0
active edge
switch bit.
When this bit is “0”, the CNTR
0
interrupt request bit is set to “1” at
the falling edge of CNTR
0
pin input signal. When this bit is “1”, the
CNTR
0
interrupt request bit is set to “1” at the rising edge of
CNTR
0
pin input signal.
(2) CNTR
0
interrupt active edge selection-2
According to the setting value of CNTR
0
active edge switch bit,
the interrupt request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀
Set the corresponding interrupt enable bit to “0” (disabled).
➁
Set the active edge switch bit.
➂
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃
Set the corresponding interrupt enable bit to “1” (enabled).
Fig. 26 Structure of timer X mode register
Fig. 27 Timer count source set register
T
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X
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b
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b
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:
T
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:
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:
E
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1
1
:
P
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N
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(
r
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t
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n
“
0
”
w
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a
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)
T
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r
X
c
o
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t
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t
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p
b
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:
C
o
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t
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t
1
:
C
o
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t
s
t
o
p
b7 b0
P
0
3
/
T
X
O
U
T
o
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p
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v
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l
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d
b
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0
:
O
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p
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t
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v
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d
(
I
/
O
p
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t
)
1
:
O
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t
p
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v
a
l
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d
(
I
n
v
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r
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C
N
T
R
0
o
u
t
p
u
t
)
b7 b0
Timer X count source selection bits
b1 b0
0 0 : f(X
IN
)/16
0 1 : f(X
IN
)/2
1 0 : f(X
IN
) (Note 1)
1 1 : Not available
Notes 1: f(X
IN
) can be used as timer X count source when using
a ceramic resonator or on-chip oscillator.
Do not use it at RC oscillation.
2: On-chip oscillator can be used when the on-chip oscillator
is enabled by bit 3 of CPUM.
Timer count source set register
(TCSS : address 002A
16
, initial value: 00
16
)
Timer B count source selection bits
b7 b6 b5
0 0 0 : f(X
IN
)/16
0 0 1 : f(X
IN
)/2
0 1 0 : f(X
IN
)/32
0 1 1 : f(X
IN
)/64
1 0 0 : f(X
IN
)/128
1 0 1 : f(X
IN
)/256
1 1 0 : Timer A underflow
1 1 1 : Not available
Timer A count source selection bits
b4 b3 b2
0 0 0 : f(X
IN
)/16
0 0 1 : f(X
IN
)/2
0 1 0 : f(X
IN
)/32
0 1 1 : f(X
IN
)/64
1 0 0 : f(X
IN
)/128
1 0 1 : f(X
IN
)/256
1 1 0 : On-chip oscillator output (Note 2)
1 1 1 : Not available