Renesas 7542 Manual Download Page 18

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7542 Group

Rev.3.02 Oct 31, 2006 Page 18 of 134
REJ03B0006-0302

Fig. 16 Memory map of special function register (SFR)

Notes 1: Do not access to the SFR area including nothing.

2: Only flash memory version has this SFR area.

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

001A

001B

001C

001D

001E

001F

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Pull-up control register (PULL)

Transmit 1 /Receive 1 buffer register (TB1/RB1)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART1 control register (UART1CON)

Baud rate generator 1 (BRG1)

Port P1P3 control register (P1P3C)

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

002C

002D

002E

002F

0030

0031

0032

0033

0034

0035

0036

0037

0038

0039

003A

003B

003C

003D

003E

003F

Timer count source set register (TCSS)

A/D conversion register (low-order) (ADL)

Prescaler 1 (PRE1)

Timer 1 (T1)

Timer X mode register

(TXM)

Prescaler X

(PREX)

Timer X

(TX)

Serial I/O2 control register (SIO2CON)

UART2 control register (UART2CON)

A/D control register (ADCON)

A/D conversion register (high-order) (ADH)

MISRG

Watchdog timer control register (WDTCON)

Interrupt edge selection register

(INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt control register 1 (ICON1)

Timer A, B mode register (TABM)

Capture/compare port register (CCPR)

Timer source selection register (TMSR)

Capture mode register (CAPM)

Compare output mode register (CMOM)

Capture/compare status register (CCSR)

Compare interrupt source set register (CISR)

Interrupt request register 2 (IREQ2)

Interrupt control register 2 (ICON2)

On-chip oscillation division ratio selection register (RODR)

Baud rate generator 2 (BRG2)

Timer A (low-order) (TAL)

Timer A (high-order) (TAH)

Timer B (low-order) (TBL)

Timer B (high-order) (TBH)

Transmit 2 / Receive 2 buffer register (TB2/RB2)

Serial I/O2 status register (SIO2STS)

Port P0P3 drive capacity control register (DCCR)

Compare register re-load register (CMPR)

Capture software trigger register (CSTR)

Capture/compare register R/W pointer (CCRP)

Compare register (high-order) (CMPH)

Compare register (low-order) (CMPL)

Capture register 1 (high-order) (CAP1H)

Capture register 1 (low-order) (CAP1L)

Capture register 0 (high-order) (CAP0H)

Capture register 0 (low-order) (CAP0L)

Interrupt source set register (INTSET)

Interrupt source discrimination register (INTDIS)

Reserved

0FE0

0FE1

Flash memory control register 0 (FMCR0) (Note 2)

Flash memory control register 1 (FMCR1) (Note 2)

0FE2

Flash memory control register 2 (FMCR2) (Note 2)

Summary of Contents for 7542

Page 1: ...issipation by an on chip oscillator connected to external ceramic resonator or quartz crystal oscillator permitting RC oscillation Watchdog timer 16 bit 1 Power source voltage XIN oscillation frequency at ceramic oscillation in double speed mode At 8 MHz 4 5 to 5 5 V XIN oscillation frequency at ceramic oscillation in high speed mode At 8 MHz 4 0 to 5 5 V At 4 MHz 2 4 to 5 5 V At 2 MHz 2 2 to 5 5 ...

Page 2: ...LK2 23 22 P0 1 LED 01 CMP 0 P0 0 LED 00 CAP 0 P3 7 LED 17 INT 0 M37542Mx XXXGP M37542MxT XXXGP M37542MxV XXXGP M37542FxGP M37542F8TGP M37542F8VGP P2 3 AN 3 P2 4 AN 4 P2 5 AN 5 V REF 2 Package type PRSP0036GA A 36P2R A 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 CNVSS XOUT XIN VSS P04 LED04 RxD2 P30 LED10 CAP1 Vcc VREF P05 LED05 TxD2 P10 RXD1 C...

Page 3: ...5 26 27 28 29 30 31 Package type PRDP0032BA A 32P4B P03 LED03 TXOUT P02 LED02 CMP1 P01 LED01 CMP0 P00 LED00 CAP0 P37 LED17 INT0 Package type PWQN0036KA A 36PJW A P07 LED07 SRDY2 P10 RxD1 CAP0 P11 TxD1 P12 SCLK1 P13 SRDY1 P14 CNTR0 P20 AN0 P21 AN1 N C P33 LED13 INT1 P32 LED12 CMP3 P31 LED11 CMP2 P30 LED10 CAP1 Vss XOUT XIN N C Vcc CNVss RESET P06 LED06 SCLK2 P3 4 LED 14 M37542Mx XXXHP M37542F8HP No...

Page 4: ... 41 40 39 37 38 CNVSS XOUT XIN VSS P04 LED04 RxD2 P30 LED10 CAP1 Vcc VREF P05 LED05 TxD2 P12 SCLK1 P25 AN5 P26 AN6 P13 SRDY1 P14 CNTR0 NC P22 AN2 NC P21 AN1 P20 AN0 P31 LED11 CMP2 P36 LED16 INT1 P23 AN3 P24 AN4 P06 LED06 SCLK2 P07 LED07 SRDY2 RESET M37542RSS NC P35 LED15 P34 LED14 P33 LED13 INT1 P32 LED12 CMP3 NC P10 RXD1 CAP0 P11 TXD1 NC NC P27 AN7 P37 LED17 INT0 P00 LED00 CAP0 P01 LED01 CMP0 P02...

Page 5: ...ion time Oscillation frequency Memory sizes Mask ROM ROM RAM FLASH ROM ROM RAM I O port P0 P1 P2 P3 Interrupts Timer Output compare Input capture Serial interface A D converter Watchdog timer Clock generating circuit Power source High speed mode At 8MHz Mask ROM voltage Middle speed mode oscillation FLASH ROM at ceramic At 4MHz Mask ROM resonance oscillation FLASH ROM At 2MHz Mask ROM oscillation ...

Page 6: ...PC L PS V SS 11 RESET 6 V CC 8 7 CNV SS P1 5 30 28 26 29 27 32 31 P2 6 P3 6 12 15 13 5 Reset input I O port P2 I O port P1 I O port P3 Clock generating circuit Clock input Clock output 9 10 4 2 3 1 A D converter 10 V REF Watchdog timer Reset 0 14 INT 0 16 17 SI O1 8 CNTR 0 I O port P0 Timer X 8 Key on wakeup Prescaler X 8 Timer B 16 P0 8 25 23 21 19 24 22 20 18 Timer 1 8 Prescaler 1 8 Timer A 16 I...

Page 7: ... RESET 13 V CC 15 14 CNV SS P1 5 3 1 35 2 36 7 6 P2 8 P3 8 21 24 22 12 Reset input I O port P2 I O port P1 I O port P3 Clock generating circuit Clock input Clock output 16 17 11 9 10 8 A D converter 10 V REF Watchdog timer Reset 0 23 INT 0 25 26 SI O1 8 CNTR 0 I O port P0 Timer X 8 Key on wakeup Prescaler X 8 Timer B 16 P0 8 34 32 30 28 33 31 29 27 Timer 1 8 Prescaler 1 8 Timer A 16 INT 1 19 20 5 ...

Page 8: ... SS 16 RESET 11 V CC 13 12 CNV SS P1 5 3 1 31 2 32 P2 6 P3 6 17 20 18 10 Reset input I O port P2 I O port P1 I O port P3 Clock generating circuit Clock input Clock output 14 15 A D converter 10 V REF Watchdog timer Reset 0 19 INT 0 21 22 SI O1 8 CNTR 0 I O port P0 Timer X 8 Key on wakeup Prescaler X 8 Timer B 16 P0 8 25 23 24 Timer 1 8 Prescaler 1 8 Timer A 16 INT 1 28 26 27 30 29 4 7 5 6 8 9 Inpu...

Page 9: ... SS 13 RESET 6 V CC 8 7 CNV SS P1 5 34 32 30 33 31 36 35 P2 6 P3 6 14 17 15 5 Reset input I O port P2 I O port P1 I O port P3 Clock generating circuit Clock input Clock output 11 12 4 2 3 1 A D converter 10 V REF Watchdog timer Reset 0 16 INT 0 20 21 SI O1 8 CNTR 0 I O port P0 Timer X 8 Key on wakeup Prescaler X 8 Timer B 16 P0 8 25 23 24 22 Timer 1 8 Prescaler 1 8 Timer A 16 Input Capture Output ...

Page 10: ...ing temperature 125 C version 2 P26 AN6 and P27 AN7 do not exist for the 32 pin version and PWQN0036KA A package so that Port P2 is a 6 bit I O port 3 P35 and P36 INT1 do not exist for the 32 pin version and PWQN0036KA A package so that Port P3 is a 6 bit I O port Capture function pin Compare function pin Timer X function pin Serial I O2 function pin Serial I O1 function pin Capture function pin S...

Page 11: ... to 16 K bytes RAM size 384 to 1024 bytes Package PRDP0032BA A 32 pin plastic molded SDIP PLQP0032GB A 0 8 mm pitch 32 pin plastic molded LQFP PRSP0036GA A 0 8 mm pitch 36 pin plastic molded SSOP PWQN0036KA A 0 5 mm pitch 36 pin plastic molded WQFN 42S1M 42 pin shrink ceramic PIGGY BACK Fig 10 Memory expansion plan 384 32K 4K ROM size bytes RAM size bytes 512 1024 16K 0 M37542F8 M37542M4 M37542M4T...

Page 12: ... temperature version Mask ROM version extended operating temperature 125 C version Mask ROM version Mask ROM version extended operating temperature version Mask ROM version extended operating temperature 125 C version Flash memory version Flash memory version Flash memory version Flash memory version Flash memory version Flash memory version extended operating temperature version Flash memory vers...

Page 13: ... Y and specifies the real address When the T flag in the processor status register is set to 1 the value contained in index register X becomes the address for the second OPERAND Stack pointer S The stack pointer is an 8 bit register used during subroutine calls and interrupts The stack is used to store the current address data and processor status when branching to subroutines or interrupt routine...

Page 14: ...L S S 1 PCL M S S S 1 S S 1 PCH M S Restore Return Address I Flag 0 to 1 Fetch the Jump Vector Store Return Address on Stack Store Contents of Processor Status Register on Stack Interrupt request Note Note The condition to enable the interrupt Interrupt enable bit is 1 Interrupt disable flag is 0 Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor st...

Page 15: ...d for decimal arithmetic 5 Break flag B The B flag is used to indicate that the current interrupt was gener ated by the BRK instruction The BRK flag in the processor status register is always 0 When the BRK instruction is used to gener ate an interrupt the processor status register is pushed onto the stack with the break flag set to 1 The saved processor status is the only place where the break fl...

Page 16: ...0 0 Single chip mode 0 1 1 0 1 1 Not available b7 b0 2 These bits are used only when a ceramic oscillation is selected Note 1 These bits can be rewritten only once after releasing reset After rewriting it is disable to write any data to bits However by reset bits are initialized and can be rewritten again It is not disable to write any data to bits for emulator MCU M37542RSS Do not use these when ...

Page 17: ...sses in the zero page area Access to this area with only 2 bytes is possible in the zero page addressing mode Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area The special page addressing mode can be used to specify memory addresses in the special page area Ac cess to this area with only 2 bytes is possible in the special page addressing mode Fig 15 Memory...

Page 18: ...rol register UART2CON A D control register ADCON A D conversion register high order ADH MISRG Watchdog timer control register WDTCON Interrupt edge selection register INTEDGE CPU mode register CPUM Interrupt request register 1 IREQ1 Interrupt control register 1 ICON1 Timer A B mode register TABM Capture compare port register CCPR Timer source selection register TMSR Capture mode register CAPM Comp...

Page 19: ...isconnected from this control and cannot exert pull up control Port P1P3 control register P1P3C By setting the port P1P3 control register address 001716 a CMOS input level or a TTL input level can be selected for ports P10 P12 P13 P36 and P37 by program Fig 19 Structure of port P1P3 control register Fig 18 Structure of pull up control register Port P1P3 control register P1P3C address 001716 initia...

Page 20: ...election register Pull up control register Port P0P3 drive capacity control register Serial I O2 control register Pull up control register Port P0P3 drive capacity control register Serial I O2 control register Interrupt edge selection register Pull up control register Port P0P3 drive capacity control register Serial I O2 control register Pull up control register Port P0P3 drive capacity control re...

Page 21: ...l up control To key input interrupt generating circuit Serial I O2 enable bit Drive capacity control P04 key on wakeup selection bit Receive enable bit 5 Port P05 Serial I O2 output Direction register Data bus Port latch Pull up control To key input interrupt generating circuit Serial I O2 enable bit Drive capacity control Transmit enable bit 6 Port P06 Serial I O2 clock output Direction register ...

Page 22: ...disable bit Direction register Serial I O1 enable bit Transmit enable bit 10 Port P12 Serial I O1 clock output Serial I O1 mode selection bit Serial I O1 enable bit Serial I O1 enable bit Serial I O1 synchronous clock selection bit Direction register Data bus Port latch Serial I O1 clock input P10 P12 P13 input level selection bit 12 Port P14 Data bus Serial I O1 ready output Port latch Direction ...

Page 23: ...l up control INT1 input control Drive capacity control INT1 input 17 Ports P34 P35 Direction register Data bus Port latch Pull up control Drive capacity control 19 Port P37 Direction register Data bus Port latch Pull up control Drive capacity control INT0 input P3 input level selection bit P10 P12 P13 P36 and P37 input level are switched to the CMOS TTL level by the port P1P3 control register When...

Page 24: ...port When selecting TxD1 function perform termination of output port When selecting external clock input perform termination of input port When selecting SRDY1 function perform termination of output port When selecting CNTR input function perform termination of input port When selecting AN function per form termination of input port When selecting CAP function per form termination of input port Wh...

Page 25: ... this register If an interrupt request of a key on wakeup UART1 bus collision detection A D conversion or timer 1 occurs an interrupt discrimi nation bit is set to 1 regardless of valid invalid state by the interrupt source set register However when the interrupt valid bit of an interrupt source set register is 0 invalid the interrupt request bit of an interrupt con trol register is not set to 1 M...

Page 26: ...en key on wakeup interrupt is enabled When UART1 bus collision detection interrupt is enabled External interrupt active edge selectable External interrupt active edge selectable External interrupt active edge selectable Compare interrupt source is selected When A D conversion interrupt is enabled STP release timer underflow When Timer 1 interrupt is enabled Non maskable software interrupt At reset...

Page 27: ...T1 bus collision detection interrupt request UART1 bus collision detection interrupt valid bit Key on wakeup interrupt request Key on wakeup interrupt valid bit Key on wakeup interrupt discrimination bit UART1 bus collision detection interrupt discrimination bit Key on wakeup UART1 bus collision detection interrupt request bit Note For key on wakeup UART1 bus collision detection A D conversion and...

Page 28: ...apture 1 interrupt request bit CNTR0 interrupt request bit Key on wake up UART1 bus collision detection interrupt request bit INT1 interrupt request bit INT0 interrupt request bit Serial I O2 transmit interrupt request bit Serial I O2 receive interrupt request bit Serial I O1 transmit interrupt request bit Interrupt source set register INTSET address 000A16 initial value 0016 Key on wakeup interru...

Page 29: ...est Port P0 Input read circuit P channel transistor for pull up CMOS output buffer PULL register bit 3 0 Port P06 latch Port P06 Direction register 1 P06 output PULL register bit 3 0 Port P05 latch Port P05 Direction register 1 P05 output PULL register bit 3 0 Port P04 latch Port P04 Direction register 1 P04 output PULL register bit 2 1 Port P03 latch Port P03 Direction register 0 P03 input PULL r...

Page 30: ... counting by software Timer X Timer X is an 8 bit timer and counts the prescaler X output When Timer X underflows the timer X interrupt request bit is set to 1 Prescaler X is an 8 bit prescaler and counts the signal selected by the timer X count source selection bit Prescaler X and Timer X have the prescaler X latch and the timer X latch to retain the reload value respectively The value of prescal...

Page 31: ...ng take the following sequence Set the corresponding interrupt enable bit to 0 disabled Set the active edge switch bit Set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed Set the corresponding interrupt enable bit to 1 enabled Fig 26 Structure of timer X mode register Fig 27 Timer count source set register Timer X mode register TXM address 002B16 initia...

Page 32: ...ister CNTR0 active edge switch bit Timer mode Pulse output mode CNTR0 active edge switch bit Timer X count source selection bits 1 1 P03 TXOUT Prescaler X latch 8 Prescaler X 8 Timer X latch 8 Timer X 8 Data bus 0 1 0 1 Writing to timer X latch Pulse output mode P03 TXOUT output valid Port P03 latch Port P03 direction register Prescaler 1 latch 8 Prescaler 1 8 Timer 1 latch 8 Timer 1 8 1 16 Data b...

Page 33: ...imer A B is executed writing to latch only or latch and timer can be selected by the setting value of the timer A B write control bit When reading from Timer A B register is executed the count value of Timer A B is read out Be sure to write to read out the low order of Timer A B and the high order of Timer A B in the following order Read Read the high order of Timer A B first and the low order of ...

Page 34: ...e to latch and timer simultaneously 1 Write to only latch Timer A count stop bit 0 Count start 1 Count stop Timer B write control bit 0 Write to latch and timer simultaneously 1 Write to only latch Timer B count stop bit 0 Count start 1 Count stop Not used return 0 when read Compare 0 1 modulation mode bit 0 Disabled 1 Enabled Compare 2 3 modulation mode bit 0 Disabled 1 Enabled b7 b0 Timer X coun...

Page 35: ...bit Compare 0 1 2 3 modulation mode In compare modulation mode modulation waveform can be gener ated by using compare channel 0 and 1 or compare channel 2 and 3 To use this mode Set 1 Enabled to the compare 0 1 2 3 modulation mode bit Set Timer A underflow for Timer B count source Set Timer A for the timer source of compare channel 0 2 Set Timer B for the timer source of compare channel 1 3 In thi...

Page 36: ...l output 1 H level output Compare 2 output status bit 0 L level output 1 H level output Compare 3 output status bit 0 L level output 1 H level output Capture 0 status bit 0 latch 00 captured 1 latch 01 captured Capture 1 status bit 0 latch 10 captured 1 latch 11 captured Not used returns 0 when read Capture Compare status register CCSR address 002216 initial value 0016 b7 b0 Compare latch 00 inter...

Page 37: ...Compare buffer 00 16 Compare latch 00 16 Compare buffer 01 16 Compare latch 01 16 Data bus Compare interrupt Compare register write pointer 001216 bits 0 to 2 Compare latch 00 01 re load bit 001416 bit 0 Timer A counter 16 Compare 0 timer source bit 001F16 bit 0 Compare 0 trigger enable bit 002116 bit 4 Output latch Compare 0 output level latch 002116 bit 0 Compare 0 output status bit 002216 bit 0...

Page 38: ...bit 1 Compare 0 trigger enable bit 002116 bit 4 Output latch Compare 0 output level latch 002116 bit 0 Compare 0 output status bit 002216 bit 0 Compare 0 output port bit 001E16 bit 2 P01 CMP0 Timer B counter 16 Compare 1 trigger enable bit 002116 bit 5 Output latch Compare 1 output level latch 002116 bit 1 Compare 1 output status bit 002216 bit 1 Underflow Compare latch 10 16 Compare buffer 10 16 ...

Page 39: ...rrupt Compare status bit Timer count clock Note Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register Re load the count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B 0000 000B 0005 0 1 1 0 000E 000C 0 Timer underflow Timer count value Compare latch 00 Compare latch 01 Compare latch 00 write Compare latch 01...

Page 40: ...A count value Compare latch 00 Compare latch 01 Compare 00 match Compare 01 match Compare 0 output Compare 0 output status bit Timer A count clock Carrier wave generated by Compare 0 Compare 0 output Timer B count value Compare latch 10 Compare latch 11 Compare 10 match Compare 11 match Compare 1 output Compare interrupt Compare 1 output status bit Timer A underflow Modulation of output waveform g...

Page 41: ... 1 output level latch is Positive Modulation output Compare 1 output Compare 0 output 2 When Compare 0 output level latch is Negative Compare 1 output level latch is Positive Modulation output Compare 1 output Compare 0 output 3 When Compare 0 output level latch is Positive Compare 1 output level latch is Negative Modulation output Compare 1 output Compare 0 output 4 When Compare 0 output level la...

Page 42: ...ts Reading from the register for each channel is controlled by setting value of the capture register read pointer Reading from each reg ister is in the following order 1 Set the value of the corresponded input capture channel to the capture register read pointer 2 Read from the capture register low order and capture register high order Notes on Input Capture If the capture trigger is input while t...

Page 43: ...ing edge 0 1 Rising edge 1 0 Falling edge 1 1 Not available Capture 0 noise filter clock selection bits b5 b4 0 0 Filter stop 0 1 f XIN 1 0 f XIN 8 1 1 f XIN 32 Capture 1 noise filter clock selection bits b7 b6 0 0 Filter stop 0 1 f XIN 1 0 f XIN 8 1 1 f XIN 32 Capture mode register CAPM address 002016 initial value 0016 b7 b0 Capture latch 00 software trigger bit Capture latch 01 software trigger...

Page 44: ...apture pointer 001316 bits 4 5 Capture latch 00 16 Capture latch 01 16 Data bus Capture interrupt Capture register 0 read pointer 001216 bit 4 Timer A counter 16 Capture 0 timer source bit 001F16 bit 4 Capture trigger Capture 0 status bit 002216 bit 4 Digital filter Ring 512 Capture latch 00 software trigger bit 001316 bit 0 Capture 0 input port bits 001E16 bits 0 1 Timer B counter 16 Capture 0 in...

Page 45: ...1 000F 1 0 1 0 1 0 Timer underflow Capture input wave Timer count value Capture latch 00 Capture latch 01 Capture interrupt Capture x x 0 1 status bit Re load the timer count value Overwrite 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B 0000 1 0 1 0 1 0 XXXX 000A 000C XXXX 0005 0001 000F Timer underflow Capture input wave Timer count value Capture latch 00 Ca...

Page 46: ...rrupt request RI Clock control circuit Shift clock Serial I O1 synchronous clock selection bit Frequency division ratio 1 n 1 Baud rate generator 1 Address 001C16 BRG count source selection bit Clock control circuit Falling edge detector Transmit buffer register 1 Data bus Address 001816 Shift clock Transmit shift completion flag TSC Transmit buffer empty flag TBE Transmit interrupt request TI Tra...

Page 47: ...er 1 Data bus Transmit shift register 1 Address 001816 Transmit shift completion flag TSC Transmit buffer empty flag TBE Transmit interrupt request TI Address 001916 ST detector SP detector UART1 control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I O1 synchronous clock selection bit Clock contr...

Page 48: ...ich are valid when asynchronous serial I O is selected and set the data format of an data transfer and one bit bit 4 which is always valid and sets the output structure of the P11 TxD1 pin Baud rate generator 1 BRG1 001C16 The baud rate generator determines the baud rate for serial transfer The baud rate generator divides the frequency of the count source by 1 n 1 where n is the value written to t...

Page 49: ...output enable bit SRDY 0 P13 pin operates as ordinary I O pin 1 P13 pin operates as SRDY1 output pin Transmit interrupt source selection bit TIC 0 Interrupt when transmit buffer has emptied 1 Interrupt when transmit shift operation is completed Transmit enable bit TE 0 Transmit disabled 1 Transmit enabled Receive enable bit RE 0 Receive disabled 1 Receive enabled Serial I O1 mode selection bit SIO...

Page 50: ...pt request issued Interrupt source set register INTSET address 000A16 initial value 0016 Key on wakeup interrupt valid bit b7 b0 0 Interrupt invalid Interrupt source discrimination register INTDIS address 000B16 initial value 0016 Key on wakeup interrupt discrimination bit b7 b0 Interrupt request register 1 IREQ1 address 003C16 initial value 0016 Serial I O1 receive interrupt request bit b7 b0 Ser...

Page 51: ...h can be selected either when the transmit buffer has emptied TBE 1 or after the transmit shift operation has ended TSC 1 by setting the transmit interrupt source selection bit TIC of the serial I O2 control register 2 If data is written to the transmit buffer register when TSC 0 the transmit clock is generated continuously and serial data is output continuously from the TxD2 pin 3 The receive int...

Page 52: ...ister 2 Data bus Transmit shift register 2 Address 002E16 Transmit shift completion flag TSC Transmit buffer empty flag TBE Transmit interrupt request TI Address 002F16 ST detector SP detector UART2 control register Address 003116 Character length selection bit Address 003016 BRG count source selection bit Transmit interrupt source selection bit Serial I O2 synchronous clock selection bit Clock co...

Page 53: ...consists of four control bits bits 0 to 3 which are valid when asynchronous serial I O is selected and set the data format of an data transfer Baud rate generator 2 BRG2 003216 The baud rate generator determines the baud rate for serial transfer The baud rate generator divides the frequency of the count source by 1 n 1 where n is the value written to the baud rate generator Notes on Serial I O2 Se...

Page 54: ...DY 0 P07 pin operates as ordinary I O pin 1 P07 pin operates as SRDY2 output pin Transmit interrupt source selection bit TIC 0 Interrupt when transmit buffer has emptied 1 Interrupt when transmit shift operation is completed Transmit enable bit TE 0 Transmit disabled 1 Transmit enabled Receive enable bit RE 0 Receive disabled 1 Receive enabled Serial I O2 mode selection bit SIOM 0 Clock asynchrono...

Page 55: ...t request bit to 1 Because the comparator is constructed linked to a capacitor set f XIN in order that the A D conversion clock is 250 kHz or over during A D conversion Notes on A D converter As for AD translation accuracy on the following operating condi tions accuracy may become low 1 Since the analog circuit inside a microcomputer becomes sen sitive to noise when VREF voltage is set up lower th...

Page 56: ...register Address 003416 Channel selector A D control circuit Resistor ladder VREF Comparator A D interrupt request b7 b0 Data bus 3 10 P20 AN0 P21 AN1 P22 AN2 P23 AN3 P24 AN4 P25 AN5 P26 AN6 P27 AN7 A D conversion register low order Address 003616 Address 003516 A D conversion register high order VSS f XIN f XIN 2 ...

Page 57: ...ernal reset occurs at the STP instruc tion execution This bit is set to 1 by program but it cannot be changed to 0 This bit is cleared to 0 after reset Notes on Watchdog Timer 1 The watchdog timer is operating during the wait mode Write data to the watchdog timer control register to prevent timer underflow 2 The watchdog timer stops during the stop mode However the watchdog timer is running during...

Page 58: ...s frequency and a CPU clock Decide on an external oscillator s oscillation stabilizing time after fully evaluating an oscillator s stabilizing time used Fig 70 Example of reset circuit Fig 71 Timing diagram at reset Note 0 2 VCC 0 V 0 V Poweron VCC RESET VCC RESET Power source voltage detection circuit Power source voltage Reset input voltage Note Reset release voltage Vcc 2 2 V Data Address 8 13 ...

Page 59: ...01B16 0016 1 1 1 0 0 0 0 0 001916 1 0 0 0 0 0 0 0 X X X 0 0 0 0 0 Address Port P1P3 control register P1P3C 14 001716 0016 Timer A B mode register TABM Capture Compare port register CCPR Timer source selection register TMSR 0016 0016 0016 001D16 001E16 001F16 0016 0016 0016 002016 002116 002216 0016 002316 35 36 37 38 39 41 42 43 44 45 Serial I O2 register SIO2CON 003116 Interrupt request register ...

Page 60: ...ion When the RC oscillation is used for the main clock connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance The frequency is affected by a capacitor a resistor and a micro computer So set the constants within the range of the frequency limits 4 External clock When the external signal clock is used for the main clock connect the XIN pin...

Page 61: ...f ceramic and RC oscillations After releasing reset the operation starts by starting an on chip os cillator Then a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register Double speed mode When a ceramic oscillation is selected a double speed mode can be used Do not use it when an RC oscillation is selected Fig 77 Structure of CPU mode register Oscillation mo...

Page 62: ...cted for CPU clock When state transition from the ceramic or RC oscillation to on chip oscillator ROSC 8 on chip oscillator middle speed mode is selected for CPU clock When the MCU operates by on chip oscillator for the main clock without external oscillation circuit connect XIN pin to VCC through a resistor and leave XOUT pin open Set 10010x002 x 0 or 1 to CPUM Fig 78 Structure of on chip oscilla...

Page 63: ...s Middle high double speed mode On chip oscillator mode 1 4 1 2 On chip oscillator division ratio selection bits ROSC 128 ROSC 8 ROSC 2 ROSC 1 RESET Although a feed back resistor exists on chip an external feed back resistor may be needed depending on conditions Note S R Q S R Q 1 2 R S Q 1 4 1 2 WIT instruction STP instruction Timing φ Internal clock STP instruction Interrupt request Reset Interr...

Page 64: ...ion from High speed mode NOP 1 Transition from Middle speed mode NOP 0 3 CPU4 12 state 3 state 4 6 When the state 3 state 2 state 1 is performed execute the NOP instruction as shown below according to the division ratio of CPU clock 1 CPUM76 002 or 012 or 112 state 3 state 2 2 NOP instruction Transition from On chip oscillator double speed mode NOP 4 Transition from On chip oscillator high speed m...

Page 65: ...stop can be confirmed by using this flag Notes on Oscillation Stop Detection Circuit Do not execute the transition to state 2 a shown in Figure 83 because in this state 2 a MCU is stopped without reset even when XIN oscillation is stopped Ceramic or RC oscillation stop detection function active bit is not cleared by the oscillation stop internal reset Accordingly the oscillation stop detection cir...

Page 66: ...abled On chip oscillator enabled RESET state 1 f XIN oscillation enabled On chip oscillator enabled Oscillation stop detection circuit is in active Note 6 Applied L to RESET pin external reset MISRG3 is cleared to 0 MISRG2 12 MISRG2 02 MISRG2 12 MISRG2 02 MISRG1 12 MISRG1 02 MISRG3 is cleared to 0 MISRG1 12 Note 3 MISRG1 02 MISRG3 is cleared to 0 State 3 State 2 f XIN oscillation enabled On chip o...

Page 67: ...ers for calculations such as ROR For setting direction registers use the LDM instruction STA in struction etc A D Conversion Do not execute the STP instruction during A D conversion Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles men tioned in the machine language instruction table The frequenc...

Page 68: ...connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring within 20mm Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions If noise having a shorter pulse width than the standard is input to the RESET pin the reset is released before the internal state of the microcomputer is completely initial ized This may cause a ...

Page 69: ...or to the Vss pin as close as possible Also connect the capacitor across the analog input pin and the Vss pin at equal length Reason Signals which is input in an analog input pin such as an A D con verter comparator input pin are usually output signals from sensor The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer the wiring to an analog...

Page 70: ...here potential levels change frequently such as the CNTR pin signal line may affect other lines at signal rising edge or falling edge If such lines cross over a clock line clock wave forms may be deformed which causes a microcomputer failure or a program runaway Keeping oscillator away from large current signal lines Installing oscillator away from signal lines where potential lev els change frequ...

Page 71: ...tchdog timer SWDT and writes the initial value N in the SWDT once at each execution of the main routine The initial value N should satisfy the following condition N 1 Counts of interrupt processing executed in each main routine As the main routine execution cycle may change because of an interrupt processing or others the initial value N should have a margin Watches the operation of the interrupt ...

Page 72: ...U rewrite and standard serial I O modes This Boot ROM area has had a standard serial I O mode control program stored in it when shipped from the factory However the user can write a rewrite control program in this area that suits the user s application sys tem This Boot ROM area can be rewritten in only parallel I O mode Item Power source voltage Vcc Temperatre at program erase Program Erase VPP v...

Page 73: ...F00016 FFFF16 32K bytes ROM Product Data block B 2K bytes Boot ROM area 4K bytes Data block A 2K bytes block 2 16K bytes block 1 8K bytes block 0 8K bytes SFR area SFR area Internal RAM area 1K bytes Internal flash memory area 4K bytes Note 3 Internal flash memory area 16K bytes Note 3 000016 004016 043F16 0FE016 RAM C00016 0FFF16 7FFF16 FFFF16 700016 SFR area 700016 780016 7FFF16 E00016 C00016 FF...

Page 74: ...e use the control program in the internal RAM for write to bit 1 To set this bit 1 to 1 it is nec essary to write 0 and then write 1 in succession to bit 1 The bit can be set to 0 by only writing 0 Bit 2 of the flash memory control register 0 is the 8KB user block E W mode enable bit By setting this bit in combination with bit 4 all user block E W enable bit of flash memory control register 2 addr...

Page 75: ...eared to 0 at the flash erasing Figure 97 shows the flash memory control register 2 Bit 0 of the flash memory control register 1 is the all user block E W enable bit By setting this bit to 0 Erase Write to all user block blocks 0 1 2 is disabled As a result error writing in program to write only to data block can be prevented Fig 96 Structure of flash memory control register 1 Fig 97 Structure of ...

Page 76: ...M area Fig 98 CPU rewrite mode set release flowchart End Start Execute read array command or reset flash memory by setting flash memory reset bit by writing 1 and then 0 in succession Note 2 Single chip mode or Boot mode Set CPU mode register Note 1 Using software command executes erase program or other operation Jump to control program transferred to internal RAM Subsequent operations are execute...

Page 77: ...le program operation data program ming and verification will start Whether the write operation is completed can be confirmed by _____ read status register or the RY BY status flag When the program starts the read status register mode is entered automatically and the contents of the status register is read at the data bus D0 to D7 The status register bit 7 SR7 is set to 0 at the same time the write...

Page 78: ... entered so that the contents of the status register can be read out The status register bit 7 SR7 is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation In this case the read status register mode remains ac tive until the read array command FF16 is written The RY BY status flag is 0 during block erase operation and 1 when th...

Page 79: ...This bit is set to 0 busy during write or erase operation and is set to 1 when these operations ends After power on the sequencer status is set to 1 ready Erase status SR5 The erase status indicates the operating status of erase operation If an erase error occurs it is set to 1 When the erase status is cleared it is reset to 0 Program status SR4 The program status indicates the operating status of...

Page 80: ...1 NO YES SR5 0 YES Erase error NO SR4 0 YES NO Command sequence error Program error End block erase program Execute the clear status register command 5016 to clear the status register Try performing the operation one more time after confirming that the command is entered correctly Should an erase error occur the block in error cannot be used Note When one of SR5 and SR4 is set to 1 none of the rea...

Page 81: ...ode protect is turned on the contents of the ROM code protect reset bits cannot be modified in parallel I O mode Use the serial I O or CPU rewrite mode to rewrite the contents of the ROM code protect reset bits Rewriting of only the ROM code protect control address address FFDB16 cannot be performed When rewriting the ROM code pro tect reset bit rewrite the whole user ROM area block 0 containing t...

Page 82: ...ten in the flash memory to see if they match If the ID codes do not match the commands sent from the programmer are not accepted The ID code consists of 8 bit data and its areas are FFD416 to FFDA16 Write a pro gram which has had the ID code preset at these addresses to the flash memory Fig 103 ID code store addresses ROM code protect control ID7 ID6 ID5 ID4 ID3 ID2 ID1 FFDB16 FFDA16 FFD916 FFD816...

Page 83: ...d Boot ROM areas shown in Figure 94 can be rewritten Both areas of flash memory can be operated on in the same way The Boot ROM area is 4 Kbytes in size and located at addresses F00016 through FFFF16 Make sure program and block erase op erations are always performed within this address range Access to any location outside this address range is prohibited In the Boot ROM area an erase block operati...

Page 84: ...s Accordingly make note of the fact that the standard serial I O mode cannot be used if the Boot ROM area is rewritten in parallel I O mode The standard serial I O mode has standard serial I O mode 1 of the clock synchronous serial and the standard serial I O mode 2 of the clock asynchronous serial Table 11 lists the description of pin function standard serial I O mode 1 Figures 104 to 106 show th...

Page 85: ...Function Apply 2 7 to 5 5 V to the Vcc pin and 0 V to the Vss pin After input of port is set input H level Reset input pin System operates when RESET pin is set to H level after CNVss pin is set to H level Connect an oscillation circuit between the XIN and XOUT pins As for the connection method refer to the clock generating circuit When system operates only by the on chip oscillator an external ci...

Page 86: ...MP3 P31 LED11 CMP2 P30 LED10 CAP1 VSS XOUT XIN 9 10 11 12 13 14 15 16 8 7 6 5 3 1 4 V CC CNV SS RESET P2 2 AN 2 P0 5 LED 05 TxD 2 20 17 18 19 21 24 P0 2 LED 02 CMP 1 P0 4 LED 04 RxD 2 P0 3 LED 03 TX OUT P0 6 LED 06 S CLK2 23 22 P0 1 LED 01 CMP 0 P0 0 LED 00 CAP 0 P3 7 LED 17 INT 0 M37542FxGP M37542F8TGP M37542F8VGP P2 3 AN 3 P2 4 AN 4 P2 5 AN 5 V REF 2 Vss BUSY H input Vcc CNVSS RESET RxD TxD SCLK...

Page 87: ...1 LED01 CMP0 P00 LED00 CAP0 P37 LED17 INT0 BUSY SCLK TXD RXD L input H input RESET Vcc Vss CNVSS Note Note Connect the oscillation circuit to XIN and XOUT 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 CNVSS XOUT XIN VSS P04 LED04 RxD2 P30 LED10 CAP1 Vcc VREF P05 LED05 TxD2 P10 RXD1 CAP0 P26 AN6 P27 AN7 P11 TXD1 P12 SCLK1 P13 SRDY1 P23 AN3 P22 AN...

Page 88: ...ter mode disconnect a wiring of a serial rewrite circuit which is for the flash memory version from the MCU by a jumper switch Connect the CNVss pin to the Vss pin with the shortest possible wiring In the normal microcomputer mode disconnect a wiring of a serial rewrite circuit which is for the flash memory version from the MCU by a jumper switch Notes 1 2 Standard serial I O mode 1 Figure 107 sho...

Page 89: ...ource RESET CNVSS P37 RP P32 CEB P07 BUSY P06 SCLK2 P05 TxD2 P04 RxD2 td port CNVSS th CNVSS RESET th CNVSS port td CNVSS RESET td RESET SCLK Symbol td port CNVss td CNVss RESET td RESET SCLK th RESET CNVss th CNVss port Ratings Unit ms ms ms ms ms Min 1 1 0 05 1 1 Typ Max 0 5 Note Keep input of P06 H until P07 turns L Note ...

Page 90: ...de 2 Function Apply 2 7 to 5 5 V to the Vcc pin and 0 V to the Vss pin After input of port is set input H level Reset input pin System operates when RESET pin is set to H level after CNVss pin is set to H level Connect an oscillation circuit between the XIN and XOUT pins As for the connection method refer to the clock generating circuit When system operates only by the on chip oscillator an extern...

Page 91: ...V CC CNV SS RESET P2 2 AN 2 P0 5 LED 05 TxD 2 20 17 18 19 21 24 P0 2 LED 02 CMP 1 P0 4 LED 04 RxD 2 P0 3 LED 03 TX OUT P0 6 LED 06 S CLK2 23 22 P0 1 LED 01 CMP 0 P0 0 LED 00 CAP 0 P3 7 LED 17 INT 0 M37542FxGP M37542F8TGP M37542F8VGP P2 3 AN 3 P2 4 AN 4 P2 5 AN 5 V REF 2 Vss H input Vcc CNVSS RESET RxD TxD BUSY L input L input Note Connect the oscillation circuit to XIN and XOUT Note Fig 109 Pin co...

Page 92: ...4 P33 LED13 INT1 P32 LED12 CMP3 P37 LED17 INT0 P00 LED00 CAP0 P01 LED01 CMP0 P02 LED02 CMP1 P03 LED03 TXOUT L input BUSY TXD RXD L input H input RESET Vcc Vss CNVSS Note Connect the oscillation circuit to XIN and XOUT Note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CNVSS P12 SCLK1 P13 SRDY1 P14 CNTR0 P20 AN0 P21 AN1 P22 AN2 P23 AN3 P24 AN4 VCC XIN XOUT VSS P11 TXD1 P10 RXD1 CAP0 P07 LED07 SRDY2 P06 LE...

Page 93: ...he flash memory version from the MCU by a jumper switch Connect the CNVss pin to the Vss pin with the shortest possible wiring In the normal microcomputer mode disconnect a wiring of a serial rewrite circuit which is for the flash memory version from the MCU by a jumper switch Notes 1 2 Fig 112 Handling example of control pins in standard serial I O mode 2 Standard serial I O mode 2 Figure 112 sho...

Page 94: ...ET CNVSS P37 RP P32 CEB P06 SCLK2 P05 TxD2 P04 RxD2 td port CNVSS th CNVSS RESET th CNVSS port td CNVSS RESET Symbol td port CNVss td CNVss RESET th RESET CNVss th CNVss port Ratings Unit ms ms ms ms Min 1 1 1 1 Typ Max Note In the standard serial I O2 set P06 and P07 as follows P06 input L level P07 BUSY signal output pin Keep open ...

Page 95: ...o VCC 0 3 0 3 to VCC 0 3 0 3 to VCC 0 3 0 3 to VCC 0 3 300 Note 20 to 85 40 to 125 Power source voltage Input voltage P00 P07 P10 P14 P20 P27 P30 P37 VREF Input voltage RESET XIN Input voltage CNVSS Output voltage P00 P07 P10 P14 P20 P27 P30 P37 XOUT Power dissipation Operating temperature Storage temperature V V V V V mW C C VCC VI VI VI VO Pd Topr Tstg Conditions Symbol Ratings Unit Parameter Al...

Page 96: ... RESET CNVSS L input voltage XIN H total peak output current Note 2 P00 P07 P10 P14 P20 P27 P30 P37 L total peak output current Note 2 P10 P14 P20 P27 L total peak output current Note 2 P00 P07 P30 P37 H total average output current Note 2 P00 P07 P10 P14 P20 P27 P30 P37 L total average output current Note 2 P10 P14 P20 P27 L total average output current Note 2 P00 P07 P30 P37 f XIN 8 MHz Mask ROM...

Page 97: ... 5 5 V Double speed mode Oscillation frequency Note 3 Mask ROM VCC 2 2 to 5 5 V at ceramic oscillation or external clock input Double speed mode Oscillation frequency Note 3 Mask ROM VCC 4 0 to 5 5 V at ceramic oscillation or external clock input FLASH ROM VCC 4 0 to 5 5 V High Middle speed mode Oscillation frequency Note 3 Mask ROM VCC 2 4 to 5 5 V at ceramic oscillation or external clock input F...

Page 98: ...0 P14 P20 P27 P30 P37 Note 1 L output voltage P00 P07 P30 P37 Drive capacity L P10 P14 P20 P27 L output voltage P00 P07 P30 P37 Drive capacity H Hysteresis CNTR0 INT0 INT1 CAP0 CAP1 Note 2 P00 P07 Note 3 Hysteresis RXD0 SCLK0 RXD1 SCLK1 Hysteresis RESET H input current P00 P07 P10 P14 P20 P27 P30 P37 H input current RESET H input current XIN L input current P00 P07 P10 P14 P20 P27 P30 P37 L input ...

Page 99: ...lator operation mode Output transistors off f XIN 8 MHz in WIT state functions except timer 1 disabled Output transistors off f XIN 2 MHz Mask ROM VCC 2 2 V FLASH ROM VCC 2 7 V in WIT state functions except timer 1 disabled Output transistors off On chip oscillator operation mode in WIT state functions except timer 1 disabled Output transistors off Increment when A D conversion is executed f XIN 8...

Page 100: ...low temperature that VREF is 3 0 V or more is recommended Electrical Characteristics of 7542 Group Flash Memory General purpose Table 21 Electrical Characteristics of 7542 Group Flash Memory General purpose Symbol Parameter Program Erase endurance Note 1 Byte program time 2Kbyte block Block erase time 8Kbyte block 16Kbyte block Time delay from suspend request until erase suspend Erase suspend requ...

Page 101: ...1 input L pulse width Note 1 Serial I O1 serial I O2 clock input cycle time Note 2 Serial I O1 serial I O2 clock input H pulse width Note 2 Serial I O1 serial I O2 clock input L pulse width Note 2 Serial I O1 serial I O2 input set up time Serial I O1 serial I O2 input hold time tW RESET tC XIN tWH XIN tWL XIN tC CNTR0 tWH CNTR0 tWL CNTR0 tC SCLK1 tWH SCLK1 tWL SCLK1 tsu RxD1 SCLK1 th SCLK1 RxD1 2 ...

Page 102: ...se width Note 2 Serial I O1 serial I O2 input set up time Serial I O1 serial I O2 input hold time tW RESET tC XIN tWH XIN tWL XIN tC CNTR0 tWH CNTR0 tWL CNTR0 tC SCLK1 tWH SCLK1 tWL SCLK1 tsu RxD1 SCLK1 th SCLK1 RxD1 2 500 200 200 1000 460 460 4000 1900 1900 800 400 µs ns ns ns ns ns ns ns ns ns ns ns Notes 1 As for CAP0 CAP1 it is the value when noise filter is not used 2 In this time bit 6 of th...

Page 103: ...1 TxD1 tr SCLK1 tf SCLK1 tr CMOS tf CMOS Serial I O1 serial I O2 clock output H pulse width Serial I O1 serial I O2 clock output L pulse width Serial I O1 serial I O2 output delay time Serial I O1 serial I O2 output valid time Serial I O1 serial I O2 clock output rising time Serial I O1 serial I O2 clock output falling time CMOS output rising time Note 1 CMOS output falling time Note 1 tC SCLK1 2 ...

Page 104: ... TxD1 tf 0 2 VCC 0 8VCC 0 8VCC tr tsu RxD1 SCLK1 th SCLK1 RxD1 tv SCLK1 TxD1 tC SCLK1 tWL SCLK1 tWH SCLK1 RXD1 at receive SCLK1 0 2VCC tWL XIN 0 8VCC tWH XIN tC XIN XIN 0 2VCC 0 8 VCC tW RESET RESET 0 2VCC tWL CNTR0 0 8VCC tWH CNTR0 tC CNTR0 TXD1 at transmit CNTR0 0 2VCC tWL CNTR0 0 8VCC tWH CNTR0 INT0 INT1 CAP0 CAP1 ...

Page 105: ...VCC 0 3 0 3 to VCC 0 3 0 3 to VCC 0 3 0 3 to VCC 0 3 300 Note 40 to 85 65 to 150 Power source voltage Input voltage P00 P07 P10 P14 P20 P27 P30 P37 VREF Input voltage RESET XIN Input voltage CNVSS Output voltage P00 P07 P10 P14 P20 P27 P30 P37 XOUT Power dissipation Operating temperature Storage temperature V V V V V mW C C VCC VI VI VI VO Pd Topr Tstg Conditions Symbol Ratings Unit Parameter All ...

Page 106: ... input level selected P10 P12 P13 P36 P37 Note 1 L input voltage RESET CNVSS L input voltage XIN H total peak output current Note 2 P00 P07 P10 P14 P20 P27 P30 P37 L total peak output current Note 2 P10 P14 P20 P27 L total peak output current Note 2 P00 P07 P30 P37 H total average output current Note 2 P00 P07 P10 P14 P20 P27 P30 P37 L total average output current Note 2 P10 P14 P20 P27 L total av...

Page 107: ...oscillation or external clock input FLASH ROM VCC 4 0 to 5 5 V Double speed mode Oscillation frequency Note 3 Mask ROM VCC 2 4 to 5 5 V at ceramic oscillation or external clock input FLASH ROM VCC 2 7 to 5 5 V Double speed mode Oscillation frequency Note 3 Mask ROM VCC 4 0 to 5 5 V at ceramic oscillation or external clock input FLASH ROM VCC 4 0 to 5 5 V High Middle speed mode Oscillation frequenc...

Page 108: ...tput voltage P00 P07 P10 P14 P20 P27 P30 P37 Note 1 L output voltage P00 P07 P30 P37 Drive capacity L P10 P14 P20 P27 L output voltage P00 P07 P30 P37 Drive capacity H Hysteresis CNTR0 INT0 INT1 CAP0 CAP1 Note 2 P00 P07 Note 3 Hysteresis RXD0 SCLK0 RXD1 SCLK1 Hysteresis RESET H input current P00 P07 P10 P14 P20 P27 P30 P37 H input current RESET H input current XIN L input current P00 P07 P10 P14 P...

Page 109: ...istors off On chip oscillator operation mode Output transistors off f XIN 8 MHz in WIT state functions except timer 1 disabled Output transistors off f XIN 2 MHz Mask ROM VCC 2 4 V FLASH ROM VCC 2 7 V in WIT state functions except timer 1 disabled Output transistors off On chip oscillator operation mode in WIT state functions except timer 1 disabled Output transistors off Increment when A D conver...

Page 110: ...low temperature that VREF is 3 0 V or more is recommended Electrical Characteristics of 7542 Group Flash Memory Extended operating temperature version Table 34 Electrical Characteristics of 7542 Group Flash Memory Extended operating temperature version Symbol Parameter Program Erase endurance Note 1 Byte program time 2Kbyte block Block erase time 8Kbyte block 16Kbyte block Time delay from suspend ...

Page 111: ...dth Note 1 CNTR0 INT0 INT1 CAP0 CAP1 input L pulse width Note 1 Serial I O1 serial I O2 clock input cycle time Note 2 Serial I O1 serial I O2 clock input H pulse width Note 2 Serial I O1 serial I O2 clock input L pulse width Note 2 Serial I O1 serial I O2 input set up time Serial I O1 serial I O2 input hold time tW RESET tC XIN tWH XIN tWL XIN tC CNTR0 tWH CNTR0 tWL CNTR0 tC SCLK1 tWH SCLK1 tWL SC...

Page 112: ...utput falling time Note 1 Note 1 Pin XOUT is excluded Table 38 Switching characteristics 2 Extended operating temperature version FLASH ROM version VCC 2 7 to 5 5V Mask ROM version VCC 2 4 to 5 5 V VSS 0 V Ta 40 to 85 C unless otherwise noted Min Typ Max Symbol Parameter Limits Unit 350 50 50 50 50 Note 1 Pin XOUT is excluded tWH SCLK1 tWL SCLK1 td SCLK1 TxD1 tv SCLK1 TxD1 tr SCLK1 tf SCLK1 tr CMO...

Page 113: ...CC td SCLK1 TxD1 tf 0 2 VCC 0 8VCC 0 8VCC tr tsu RxD1 SCLK1 th SCLK1 RxD1 tv SCLK1 TxD1 tC SCLK1 tWL SCLK1 tWH SCLK1 RXD1 at receive SCLK1 0 2VCC tWL XIN 0 8VCC tWH XIN tC XIN XIN 0 2VCC 0 8 VCC tW RESET RESET 0 2VCC tWL CNTR0 0 8VCC tWH CNTR0 tC CNTR0 TXD1 at transmit CNTR0 0 2VCC tWL CNTR0 0 8VCC tWH CNTR0 INT0 INT1 CAP0 CAP1 ...

Page 114: ...125 Note 2 65 to 150 Power source voltage Input voltage P00 P07 P10 P14 P20 P27 P30 P37 VREF Input voltage RESET XIN Input voltage CNVSS Output voltage P00 P07 P10 P14 P20 P27 P30 P37 XOUT Power dissipation Operating temperature Storage temperature V V V V V mW C C VCC VI VI VI VO Pd Topr Tstg Conditions Symbol Ratings Unit Parameter All voltages are based on VSS When an input voltage is measured ...

Page 115: ...age TTL input level selected P10 P12 P13 P36 P37 Note 1 L input voltage RESET CNVSS L input voltage XIN H total peak output current Note 2 P00 P07 P10 P14 P20 P27 P30 P37 L total peak output current Note 2 P10 P14 P20 P27 L total peak output current Note 2 P00 P07 P30 P37 H total average output current Note 2 P00 P07 P10 P14 P20 P27 P30 P37 L total average output current Note 2 P10 P14 P20 P27 L t...

Page 116: ...ramic oscillation or external clock input FLASH ROM VCC 4 0 to 5 5 V Double speed mode Oscillation frequency Note 3 Mask ROM VCC 2 4 to 5 5 V at ceramic oscillation or external clock input FLASH ROM VCC 2 7 to 5 5 V Double speed mode Oscillation frequency Note 3 Mask ROM VCC 4 0 to 5 5 V at ceramic oscillation or external clock input FLASH ROM VCC 4 0 to 5 5 V High Middle speed mode Oscillation fr...

Page 117: ... 5 H output voltage P00 P07 P10 P14 P20 P27 P30 P37 Note 1 L output voltage P00 P07 P30 P37 Drive capacity L P10 P14 P20 P27 L output voltage P00 P07 P30 P37 Drive capacity H Hysteresis CNTR0 INT0 INT1 CAP0 CAP1 Note 2 P00 P07 Note 3 Hysteresis RXD0 SCLK0 RXD1 SCLK1 Hysteresis RESET H input current P00 P07 P10 P14 P20 P27 P30 P37 H input current RESET H input current XIN L input current P00 P07 P1...

Page 118: ... transistors off On chip oscillator operation mode Output transistors off f XIN 8 MHz in WIT state functions except timer 1 disabled Output transistors off f XIN 2 MHz Mask ROM VCC 2 4 V FLASH ROM VCC 2 7 V in WIT state functions except timer 1 disabled Output transistors off On chip oscillator operation mode in WIT state functions except timer 1 disabled Output transistors off Increment when A D ...

Page 119: ... low temperature that VREF is 3 0 V or more is recommended Electrical Characteristics of 7542 Group Flash Memory Extended operating temperature 125 C version Table 45 Electrical Characteristics of 7542 Group Flash Memory Extended operating temperature 125 C version Symbol Parameter Program Erase endurance Note 1 Byte program time 2Kbyte block Block erase time 8Kbyte block 16Kbyte block Time delay ...

Page 120: ...H pulse width Note 1 CNTR0 INT0 INT1 CAP0 CAP1 input L pulse width Note 1 Serial I O1 serial I O2 clock input cycle time Note 2 Serial I O1 serial I O2 clock input H pulse width Note 2 Serial I O1 serial I O2 clock input L pulse width Note 2 Serial I O1 serial I O2 input set up time Serial I O1 serial I O2 input hold time tW RESET tC XIN tWH XIN tWL XIN tC CNTR0 tWH CNTR0 tWL CNTR0 tC SCLK1 tWH SC...

Page 121: ...utput falling time Note 1 Note 1 Pin XOUT is excluded Table 49 Switching characteristics 2 Extended operating temperature 125 C version FLASH ROM version VCC 2 7 to 5 5V Mask ROM version VCC 2 4 to 5 5 V VSS 0 V Ta 40 to 125 C unless otherwise noted Min Typ Max Symbol Parameter Limits Unit 350 50 50 50 50 Note 1 Pin XOUT is excluded tWH SCLK1 tWL SCLK1 td SCLK1 TxD1 tv SCLK1 TxD1 tr SCLK1 tf SCLK1...

Page 122: ... 2VCC td SCLK1 TxD1 tf 0 2 VCC 0 8VCC 0 8VCC tr tsu RxD1 SCLK1 th SCLK1 RxD1 tv SCLK1 TxD1 tC SCLK1 tWL SCLK1 tWH SCLK1 RXD1 at receive SCLK1 0 2VCC tWL XIN 0 8VCC tWH XIN tC XIN XIN 0 2VCC 0 8 VCC tW RESET RESET 0 2VCC tWL CNTR0 0 8VCC tWH CNTR0 tC CNTR0 TXD1 at transmit CNTR0 0 2VCC tWL CNTR0 0 8VCC tWH CNTR0 INT0 INT1 CAP0 CAP1 ...

Page 123: ...eters Symbol Reference 7 1 7 0 6 9 D 7 1 7 0 6 9 E 1 4 A2 9 2 9 0 8 8 9 2 9 0 8 8 1 7 A 0 2 0 1 0 0 7 0 5 0 3 L x 8 0 c 0 8 e 0 10 y HD HE A1 bp b1 c1 ZD ZE L1 Terminal cross section b1 c 1 bp c y Index mark 1 18 19 36 F 1 2 3 E H E D e bp A c Detail F A2 L A1 INCLUDE TRIM OFFSET DIMENSION 3 DOES NOT NOTE DO NOT INCLUDE MOLD FLASH DIMENSIONS 1 AND 2 1 2 Previous Code JEITA Package Code RENESAS Cod...

Page 124: ... 22 0 27 0 34 P SDIP32 8 9x28 1 78 2 2g MASS Typ 32P4B PRDP0032BA A RENESAS Code JEITA Package Code Previous Code bp 0 35 0 45 0 55 10 16 9 86 10 46 b2 0 63 0 73 1 03 A2 3 8 0 1 528 2 028 e1 e 1 Previous Code JEITA Package Code RENESAS Code PWQN0036KA A 36PJW A MASS Typ 0 07g P HWQFN36 6x6 0 50 0 7 0 6 0 5 0 25 0 2 0 15 Max Nom Min Dimension in Millimeters Symbol Reference 6 1 6 0 5 9 D 6 1 6 0 5 ...

Page 125: ...direct address 4 Multiplication and Division Instructions 1 The index X mode T and the decimal mode D flags do not affect the MUL and DIV instruction 2 The execution of these instructions does not change the con tents of the processor status register Set D flag to 1 ADC or SBC instruction NOP instruction SEC CLC or CLD instruction Fig 3 Status flag at decimal calculations 2 Decimal calculations 1 ...

Page 126: ... Notes in stand by state In stand by state 1 for low power dissipation do not make input levels of an input port and an I O port undefined Pull up connect the port to Vcc or pull down connect the port to Vss these ports through a resistor When determining a resistance value note the following points External circuit Variation of output levels during the ordinary operation When using a built in pul...

Page 127: ... direction register setup changes for the output mode be cause of a program runaway or noise a short circuit may occur 3 Do not connect multiple ports in a lump to VCC or VSS through a resistor Reason If the direction register setup changes for the output mode be cause of a program runaway or noise a short circuit may occur between ports Notes on Interrupts 1 Change of relevant register settings W...

Page 128: ...edge of CNTR0 pin input signal 2 Timer X count source selection The f XIN frequency not divided can be selected by the timer X count source selection bits bits 1 and 0 of timer count source set register address 2A16 only when the ceramic oscillation or the on chip oscillator is selected Do not select it for the timer X count source at the RC oscillation 3 Pulse output mode Set the direction regist...

Page 129: ...e is changed between high order reading and low order reading Accordingly some countermeasure by software is recommended for ex ample comparing the values that twice of read 2 Timer A cannot be used for the capture source timer in the fol lowing state XIN oscillation selected by clock division ratio selection bits bits 7 and 6 of CPU mode register address 3B16 Timer A count source On chip oscillat...

Page 130: ...ta reception Accordingly the transmission circuit does not stop by clearing only the transmit enable bit to 0 transmit disabled Also the transmission circuit cannot be initialized even if the serial I Oi enable bit is cleared to 0 serial I Oi disabled same as 1 4 When signals are output from the SRDYi pin on the reception side by using an external clock set all of the receive enable bit the SRDYi ...

Page 131: ...cted it functions P13 pin It can be used as a normal I O pin Note on Bus Collision Detection When serial I O1 is operating at half duplex communication set bus collision detection interrupt to be disabled Notes on Serial I O2 1 I O pin function when serial I O2 is enabled The pin functions of P06 SCLK2 and P07 SRDY2 are switched to as follows according to the setting values of a serial I O2 mode s...

Page 132: ... RESET pin and the Vss pin And use a 1000 pF or more capacitor for high frequency use When connecting the capacitor note the following Make the length of the wiring which is connected to a capacitor as short as possible Be sure to verify the operation of application products on the user side Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin it may cause ...

Page 133: ...se constants such as capacitance depend on the resonator 7 RC oscillation When the RC oscillation is used for the main clock connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance The frequency is affected by a capacitor a resistor and a micro computer So set the constants within the range of the frequency limits 8 External clock When th...

Page 134: ...timer has been already activated internal reset due to an underflow will not occur because the watchdog timer is surely initialized during program or erase 5 Reset Reset is always valid The MCU is activated using the boot mode at release of reset in the condition of CNVss H so that the pro gram will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area Electric C...

Page 135: ...CPU mode register added Fig 37 and Fig 38 Pin name added Fig 39 Pin name added Fig 46 and Fig 47 Pin name added A D Converter revised Fig 70 Flash memory control register 2 added Fig 79 5 6 revised A D Converter revised DATA REQUIRED FOR MASK ORDERS revised Description of flash memory control register 0 bit 2 Fig 83 revised Description of flash memory control register 2 Fig 85 and Table 8 added Fi...

Page 136: ... end of this data sheet Part name revised 36PJW A package added APPENDIX added FEATURES Programmable I O ports A D converter Description added Fig 4 Pin 1 to Pin 3 revised M37542F8HP Note added Table 2 M37542F8HP Note added Notes on A D conversion added Table 7 Number of program erase times revised Fig 110 Figure title and table in figure revised and Note added M37542F8HP Note added Notes on A D a...

Page 137: ...P M37542F4GP M37542F4FP M37542F4SP added Table 15 Conditions Description added Table 18 Note 1 added Table 20 Fig 104 added Table 28 Conditions Description added Table 31 Note 1 added Table 34 Fig 106 added Extended operating temperature 125 C version added 2 How to reference the processor status register revised Fig 2 revised Package revised 1 2 3 5 10 11 12 21 24 46 53 54 60 63 72 73 77 86 87 91...

Page 138: ...e revised and note 2 added 17 ROM Description added Fig 15 Note 2 added 24 Table 7 XIN and XOUT added 57 132 Notes on Watchdog Timer Note 3 revised 71 5 Setup for I O ports Note eliminated 73 Fig 94 Block diagram revised and note 3 added 125 4 BRK instruction eliminated 132 1 Analog input pin Description revised ...

Page 139: ...bility for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications 9 You should use the products described herein within the ran...

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