RTL8201(L)
2002-01-18
Rev.1.04
21
7.7 Power Down, Link Down, Power Saving, and Isolation Modes
The RTL8201(L) supplies 4 kinds of Power Saving mode operation. This section will discuss all four, including how to
implement each mode. The first three modes are configured through software, and the fourth through hardware.
1)
Analog off
: Setting bit 11 of register 17 to 1 will put the RTL8201(L) into analog off state. In analog off state, the
RTL8201(L) will power down all analog functions such as transmit, receive, PLL, etc. However, the internal 25Mhz
crystal oscillator will not be powered down. The digital functions in this mode are still available which allows
reacquisition of analog functions.
2)
LDPS mode
: Setting bit 12 of register 17 to 1 or pulling the LDPS pin high will put the RTL8201(L) into LDPS (Link
Down Power Saving) mode. In LDPS mode, the RTL8201(L) will detect the link status to decide whether or not to turn
off the transmit function. If the link is off, FLP or 100Mbps IDLE/10Mbps NLP will not be transmitted. However, some
signals similar to NLP will be transmitted. Once the receiver detects any leveled signals, it will stop the signal and
transmit FLP or 100Mbps IDLE/10Mbps NLP again. This may save about 60%~80% power when the link is down.
3)
PWD mode
: Setting bit 11 of register 0 to 1 will put the RTL8201(L) into power down mode. This is the maximum power
saving mode while the RTL8201(L) is still alive. In PWD mode, the RTL8201(L) will turn off all analog/digital functions
except the MDC/MDIO management interface. Therefore, if the RTL8201(L) is put into PWD mode and the MAC wants
to recall the PHY, it must create the MDC/MDIO timing by itself (this is done by software).
4)
Isolation mode
: This mode is different from the three previous software configured power saving modes. This mode is
configured by hardware pin 43. Setting pin 43 high will isolate the RTL8201(L) from the Media Access Controller (MAC)
and the MDC/MDIO management interface. In this mode, power consumption is minimum.
7.8 Media Interface
7.8.1 100Base Tx/Rx
1)
100Base Transmit Function:
The 100Base transmit function is performed as follows: First the transmit data in 4 bits
nibbles (TXD[0..3]), clocked in 25MHz (TXC) will be transformed into 5B symbol code, called 4B/5B encoding.
Scrambling, serializing and conversion to 125Mhz, and NRZ to NRZI will then take place. After this process, the NRZI
signal will pass to the MLT3 encoder, then to the transmit line driver. The transmitter will first assert TXEN. Before
transmitting the data pattern, it will send a /J/K/ symbol (Start-of-frame delimiter), the data symbol, and finally a /T/R/
symbol known as the End-Of-Frame delimiter. The 4B/5B and the scramble process can be bypassed by setting the PHY
register. For better EMI performance consideration, the seed of the scrambler is related to the PHY address. Therefore in a
hub/switch environment, every RTL8201(L) will be set into a different PHY address so that they will use different
scrambler seeds, which will spread the output of the MLT3 signals.
2)
100Base Receive Function:
The 100Base receive function is performed as follows: The received signal will first be
compensated by the adaptive equalizer to make up for the signal loss due to cable attenuation and ISI. The Baseline
Wander Corrector will monitor the process and dynamically apply corrections to the process of signal equalization. The
PLL will then recover the timing information from the signals and form the receive clock. With this, the received signal
may be sampled to form NRZI data. The next steps are the NRZI to NRZ process, unscrambling of the data, serial to
parallel and 5B to 4B conversion and passing of the 4B nibble to the MII interface.
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