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RTL8201(L)

 

2002-01-18

 

 

Rev.1.04 

 

 

6.2 Register 1 Basic Mode Status   

Address 

Name 

Description/Usage 

Default/Attribute 

1:<15> 100Base-T4 

100Base_T4:

 The RTL8201L supports the 100Base-T4 function. If the 

chip is set to operate in this mode, this bit will return a ‘1’ when read. 
1: Enable 100Base-T4 support 
0: Suppress 100Base-T4 support 

0, RO 

1:<14> 100Base_TX_ 

FD 

100Base_TX_FD:

 The RTL8201L is capable of operating in 

100Base-TX full duplex mode. If the chip is set to operate in this mode, 
this bit will return a ‘1’ when read. 
1: Enable 100Base-TX full duplex support 
0: Suppress 100Base-TX full duplex support 

1, RO 

1:<13> 100BASE_TX_

HD 

100Base_TX_HD:

 The RTL8201L is capable of operating in 

100Base-TX half duplex mode. If the chip is set to operate in this mode, 
this bit will return a ‘1’ when read. 
1: Enable 100Base-TX half duplex support 
0: Suppress 100Base-TX half duplex support 

1, RO 

1:<12> 10Base_T_FD 

10Base_T_FD:

 The RTL8201L is capable of operating in 10Base-T full 

duplex mode. If the chip is set to operate in this mode, this bit will 
return a ‘1’ when read. 
1: Enable 10Base-T full duplex support 
0: Suppress 10Base-T full duplex support 

1, RO 

1:<11> 10_Base_T_HD 

10Base_T_HD:

 The RTL8201L is capable of operating in 10Base-T 

half duplex mode. If the chip is set to operate in this mode, this bit will 
return a ‘1’ when read. 
1: Enable 10Base-T half duplex support 
0: Suppress 10Base-T half duplex support 

1, RO 

1:<10:6> Reserved 

Reserved:

 Ignore the output of the RTL8201L when these bits are 

read. 

 

1:<5> Auto 

Negotiation  

Complete 

Auto-negotiate Complete:

 Bit 5 will return a ‘1’ if the 

Auto-negotiation process has been completed and the contents of 
registers 4 and 5 are valid. 
1: Auto-negotiation process completed 
0: Auto-negotiation process not completed 

0, RO 

1:<4> Remote 

Fault 

Remote Fault:

 The PHY will return a ‘1’ in bit 4 when its Link Partner 

has signaled a far-end fault condition. When a far end fault occurs, the bit 
will be latched at ‘1’ and will remain so until the register is read and the 
remote fault condition has been cleared. 
1: Remote fault condition detected (cleared on read) 
0: No remote fault condition detected 
When in 100Base-FX mode, this bit means an in-band signal 
Far-End-Fault is detected. 

0, RO   

1:<3> Auto 

Negotiation 

Auto-Negotiation Ability:

 The RTL8201L is capable of performing 

IEEE Auto-negotiation, and will return a ‘1’ when bit 4 is read, 
regardless of whether or not the Auto-negotiation function has been 
disabled. 
1: Link had not been experienced fail state 
0: Link had been experienced fail state 

1, RO   

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Summary of Contents for RTL8201(L)

Page 1: ...X_ER Counter REC 15 6 11 Register1910MbpsNetworkInterfaceConfiguration 15 6 12 Register 20 PHY 1_1 15 6 13 Register 21 PHY 1_2 16 6 13 Register 22 PHY 2 16 6 14 Register 23 Twister_1 16 6 15 Register...

Page 2: ...Interface interface Flow control ability support to co work with MAC by MDC MDIO 48 pin LQFP package 2 General Description The RTL8201 L is a single port Phyceiver with an MII Media Independent Inter...

Page 3: ...l to Serial Baseline wander Correction 5B 4B Decoder Data Alignment Descrambler 4B 5B Encoder Scrambler 10 100 half full Switch Logic 10 100M Auto negotiation Control Logic Manchester coded waveform 1...

Page 4: ...X2 33 TPTX 34 TPTX 28 RTSET 31 TPRX 30 TPRX 43 ISOLATE 40 RPTR RTT2 39 Speed 38 Duplex 37 ANE 41 LDPS 44 MII SNIB 9 LED0 PAD0 10 LED1 PAD1 12 LED2 PAD2 13 LED3 PAD3 15 LED4 PAD4 27 RTT3 VCTRL 42 RESET...

Page 5: ...e Data These are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the RXC for reception by the external physical unit PHY RXER O 24 Receive error if any 5B...

Page 6: ...Interface PHY Address Config Symbol Type Pin s No Description LED0 PAD0 O 9 Link LED LED1 PAD1 O 10 Full Duplex LED LED2 PAD2 O 12 Link 10 ACT LED LED3 PAD3 O 13 Link 100 ACT LED LED4 PAD4 O 15 Colli...

Page 7: ...ompleted which requires approximately 1us Writing a 0 to this bit has no effect Because this bit is self clearing after a few cycles from a write operation it will return a 0 when read 1 Software rese...

Page 8: ...1 Power down 0 Normal operation 0 RW 0 10 Reserved Reserved Ignore the output of the RTL8201L when these bits are read 0 9 Restart Auto Negotiation Restart Auto Negotiation Bit 9 is a self clearing b...

Page 9: ...Base T half duplex mode If the chip is set to operate in this mode this bit will return a 1 when read 1 Enable 10Base T half duplex support 0 Suppress 10Base T half duplex support 1 RO 1 10 6 Reserved...

Page 10: ...lity registers and will return a 1 when bit 0 is read Several extended registers have been implemented in the RTL8208 and their bit functions are defined later in this section 1 Extended register capa...

Page 11: ...ility to the Link Partner that the RTL8201L can operate in 100Base T4 mode Writing a 0 to this bit will suppress the transmission of this ability to the Link Partner Resetting the chip will restore th...

Page 12: ...ities of the Link Partner as received during Auto negotiation The content changes after the successful Auto negotiation if Next pages are supported Address Name Description Usage Default Attribute 5 1...

Page 13: ...or the RTL8201L is reset 1 10Base T full duplex is supported by link partner 0 10Base T full duplex not supported by link partner 0 RO 5 5 10 10Base T This bit indicates that the Link Partner can supp...

Page 14: ...O 6 1 PAGE_RX Page Received This bit is set high when a new Link Code Word Page has been received from the Link Partner checked and acknowledged This bit is cleared when the link is lost or the chip i...

Page 15: ...causes a pre mature end error detection to be reported 0 RW 17 2 LINK_err Assertion of this bit causes a link error detection to be reported 0 RW 17 1 PKT_err Assertion of this bit causes a detection...

Page 16: ...h test functions as RTL8139C 76 RO 22 7 0 PHY2_80 PHY2 register for PLL select functions as RTL8139C 80 R W 6 14 Register 23 Twister_1 Address Name Description Usage Default Attribute 23 15 0 TW_1 Twi...

Page 17: ...d receive function While transmitting packets the MAC will first assert the TXEN signal and change byte data into 4 bits nibble and pass to the PHY by TXD 0 3 PHY will sample TXD 0 synchronously with...

Page 18: ...EED DUX pins and their operation mode ANE SPEED DUX Operation H L L Auto negotiation enabled the ability field does not support 100Mbps or full duplex mode operation H L H Auto negotiation enabled the...

Page 19: ...h is the default mode for the RTL8201 This pin pulled low will set the RTL8201 L into SNI mode operation When set to SNI mode the RTL8201 L will work at 10Mbps Please refer to the section covering Ser...

Page 20: ...d PHY address configurations In the left figure the PHY address is set to 00001b 01h In the right figure the PHY address is set to 00010b 02h In the above two PHY address designs all useable LEDs have...

Page 21: ...s configured by hardware pin 43 Setting pin 43 high will isolate the RTL8201 L from the Media Access Controller MAC and the MDC MDIO management interface In this mode power consumption is minimum 7 8...

Page 22: ...using the RTL8201 L in a NIC or switch application please set the default mode NIC Switch mode is the default setting and has the RPTR pin pulled low or bit 15 of register 17 is set to 0 7 10 Reset P...

Page 23: ...mode 8 mA PPWD Power down mode 6 mA PIsolate Isolate mode 5 mA P100F 100Base full duplex 99 mA P10F 10Base full duplex 129 mA P10TX 10Base transmit 127 mA P10RX 10Base receive 32 mA P10IDLE 10Base id...

Page 24: ...on Without Collision Shown is an example transfer of a packet from MAC to PHY 8 2 2 Reception Without Error Shown is an example of transfer of a packet from PHY to MAC Tel 49 0 234 9351135 Fax 49 0 23...

Page 25: ...11 0 15 0 22 0 29 between 0 10 mm and 0 25 mm from the lead tip b1 0 006 0 008 0 010 0 15 0 20 0 25 6 A1 is defined as the distance from the seating plane to the c 0 004 0 008 0 09 0 20 lowest point o...

Page 26: ...eadquarters 1F No 2 Industry East Road IX Science based Industrial Park Hsinchu 300 Taiwan R O C Tel 886 3 5780211 Fax 886 3 5776047 WWW www realtek com tw Tel 49 0 234 9351135 Fax 49 0 234 9351137 E...

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