RTL8201(L)
2002-01-18
Rev.1.04
10
1:<2> Link
Status
Link Status:
The RTL8201L will return a ‘1’ on bit 2 when the link
state machine is in Link Pass, indicating that a valid link has been
established. Otherwise, it will return ‘0’. When a link failure occurs
after the link pass state has been entered, the Link Status bit will be
latched at ‘0’ and will remain so until the bit is read. After the bit is
read, it becomes ‘1’ if the Link Pass state has been entered again.
1: Valid link established
0: No valid link established
0, RO
1:<1> Jabber
Detect
Jabber Detect:
The RTL8201L will return a ‘1’ on bit 1 if a jabber
condition has been detected. After the bit is read, or if the chip is reset,
it reverts to ‘0’. This is for 10Base-T only.
1: Jabber condition detected
0: No jabber condition detected
0, RO
1:<0> Extended
Capability
Extended Capability:
The RTL8201L supports extended capability
registers, and will return a ‘1’ when bit 0 is read. Several extended
registers have been implemented in the RTL8208, and their bit functions
are defined later in this section.
1: Extended register capability
0: Basic register capability only
1, RO
6.3. Register 2 PHY Identifier 1
The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY section of this device. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model
revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier
is intended to support network management.
Address
Name
Description/Usage
Default/Attribute
2:<15;0>
PHYID1
PHY identifier ID for software recognize RTL8201
0000, RO
6.4. Register 3 PHY Identifier 2
Address
Name
Description/Usage
Default/Attribute
3:<15;0>
PHYID2
PHY identifier ID for software recognize RTL8201
8201, RO
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