Realtek RTD2120K, Manual

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Realtek RTD2120-series
confidential 21
Name Bits Read/Write Reset State Comments
ADC1_CONV
_DATA 7:2 R 3F Converted data of ADC1
reserved 1:0 -- 00
Register::ADC2_convert_result 0xFF0E
Name Bits Read/Write Reset State Comments
ADC2_CONV
_DATA 7:2 R 3F Converted data of ADC2
reserved 1:0 -- 00
Register::ADC3_convert_result 0xFF0F
Name Bits Read/Write Reset State Comments
ADC3_CONV
_DATA 7:2 R 3F Converted data of ADC3
reserved 1:0 -- 00
PLL
RTD2120 contains a PLL to make the whole chip operate at higher or lower speed for different
demands. After reset, RTD2120 uses crystal frequency as the system clock. User can program the PLL
to operate at the desired frequency and select system clock to PLL output by setting MCU_CLK_SEL.
RTD2120 will switch system clock to PLL output only when PLL is stable. Moreover, the divider is
glitch free so user can modify its value at any time.For normal operation, user must choose the crystal
whose frequency is between 11M and 27MHz . Besides, VCO frequency must be programmed
between 40M and 80MHz.
Note: Fvco = Xtal *
(M/N) , where M=1, N=1.
Crystal
11M~27MHz
N
DIV
PFD VCO
M
40M~80MHz
PUMP
MCU_CLK_SEL
MCU_CLK