Realtek RTD2120-series
confidential
25
D_DDC_EN
0
R/W
0
DVI DDC Channel Enable Switch
0: MCU access Enable
1: External DDC access Enable
Register::DVI_DDC_control
0xFF24
Name
Bits
Read/Write
Reset State
Comments
D_DBN_CLK
_SEL
7:6
R/W
0
De-bounce clock divider
00: 1/1 reference clock
01: 1/2 reference clock
1X: 1/4 reference clock
D_STOP_DB
N_SEL
5:4
R/W
0
De-bounce sda stage
0X: latch one stage
10: latch two stage
11: latch three stage
D_SYS_CK_S
EL
3
R/W
0
De-bounce reference clock
0: crystal clock
1: PLL clock
D_DDC2
2
R/W
0
Force to DVI DDC to DDC2 mode
0: Normal operation
1: DDC2 is active
RST_D_DDC
1
R/W
0
Reset DVI DDC circuit
0: Normal operation
1: reset (auto cleared)
RVT_D_DDC
1_EN
0
R/W
0
DVI DDC revert to DDC1 enable(SCL idle
for 128 VSYNC)
0: Disable
1: Enable
Register::DDCRAM_partition
0xFF26
Name
Bits
Read/Write
Reset State
Comments
reserved
7:3
--
00
Reserved
VS_CON
2
R/W
0
0: VSYNC signal is connected to ADC DDC
1: VSYNC signal is connected to DVI DDC
DDCRAM_SI
Z
1:0
R/W
0
0x:ADC DDCRAM=128 byte, DVI
DDCRAM=128 byte
10:ADC DDCRAM=0 byte, DVI
DDCRAM=256 byte
11:ADC DDCRAM=256 byte, DVI
DDCRAM=0 byte
IIC Interface
Register::IIC_set_slave
0xFF27
