Realtek RTD2120K Manual Download Page 19

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Realtek RTD2120-series

confidential

Register::Port67_pin_reg

0xFF5F

Name

Bits

Read/Write

Reset State

Comments

Reserved

7:1

Reserved

P67

R/W

Input/output value of P6.7

Register::Port76_pin_reg

0xFF60

Name

Bits

Read/Write

Reset State

Comments

Reserved

7:1

Reserved

P76

R/W

Input/output value of P7.6

Register::Port77_pin_reg

0xFF61

Name

Bits

Read/Write

Reset State

Comments

Reserved

7:1

Reserved

P77

R/W

Input/output value of P7.7

Low Voltage Reset & Power on Reset

When the voltage level of power supply is below V

, the low voltage reset(LVR) generates a chip

reset signal. After the power supply is above V

(2.6V), LVR remain in reset state for 65536 X

’

tal

cycle(t

POR

) to guarantee the chip exit reset condition.

POR

VCC

VSS

INTERNAL RESET

Register::LVR_control

0xFF0A

Name

Bits

Read/Write

Reset State

Comments

Summary of Contents for RTD2120K

Page 1: ...Realtek RTD2120 series confidential 1 RTD2120 series 8051 Embedded Micro Controller for Monitor Fully Technology Revision Version 1 06 Last updated 2007 4 3 ...

Page 2: ...3 1 revise the SFR table à delete address 93 B3 2 add PWM description 3 add power supply current 4 add description All NC pin must be left unconnected or be connected to GND 2006 8 1 1 04 1 added RTD2120K QFP44 pin config 2 added RTD2120K QFP44 pin description 2007 1 16 1 05 1 added reset pulse minimum length is 16 MCU clk cycle page 10 2007 2 9 1 06 1 modified WDT block diagram 2007 4 3 ...

Page 3: ...Hz l 4 clocks per machine cycle l 256 byte internal RAM l 512 byte external data RAM including 256 byte DDC RAM 128 byte x 2 and 256 byte general purpose RAM l 96K byte flash memory 64k for program and 32k for saving parameter l Two DDC ports compliant with VESA DDC1 2B 2Bi CI l Three channels of PWM DAC with programmable frequency from 100K to 100Hz l Watchdog timer with programmable interval l T...

Page 4: ... 19 18 40 41 42 43 44 1 2 3 4 5 6 8 7 10 9 12 11 14 13 16 15 17 38 39 36 37 34 35 32 33 30 31 29 RTD2120S 44 PIN PLCC 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 43 44 45 46 47 48 2 1 4 3 6 5 8 7 10 9 11 35 36 33 34 31 32 29 30 27 28 26 RTD2120L 48 PIN LQFP 42 37 12 24 25 P5 5 PWM5 DSCL P5 6 DSDA P5 7 RST ASCL P3 0 RXD ASDA P3 1 TXD P3 2 INT0 P3 3 INT1 P3 4 T0 P3 5 T1 P6 4 P1 4 P1 5 P1 6 P1 7 NC ...

Page 5: ... P1 5 P1 6 P1 7 NC NC NC VSYNC P6 7 P6 6 CLKO1 P6 5 P6 3 ADC3 P6 2 ADC2 P6 1 ADC1 P6 0 ADC0 NC VSS XI XO P7 7 P7 6 CLKO2 P1 3 P1 2 P1 0 T2 VCC NC P5 0 PWM0 P5 1 PWM1 P5 2 PWM2 P5 3 PWM3 P5 4 PWM4 P1 1 NC 22 21 20 19 18 17 16 15 14 13 12 2 1 4 3 6 5 8 7 10 9 11 32 33 30 31 28 29 26 27 24 25 23 RTD2120K 44 PIN QFP 34 35 36 37 38 39 40 41 42 43 44 ...

Page 6: ...enerator XFR register FF00 FFFF TSMC FLASH 96K byte MEM_bus Internal RAM 256 byt e IRAM_bus DW8051_core DDC_RAM1 128 byte DDC_RAM2 128 byte Routing Box FLASH ISP interface Watch dog timer Interrupt Controller PLL clock gen Timer 2 Timer 0 Timer 1 Serial port 0 XTAL External RAM Interface External RAM 256 byte F900 F97F F980 F9FF F800 F8FF 00 FF GPIO ...

Page 7: ...Open Drain General purpose I O DVI DDC SCL 9 3 3 P5 7 DSDA I O 1 P5 7 Open Drain General purpose I O DVI DDC SDA 10 4 4 RST I Down 0 Input High active RESET 11 5 5 ASCL P3 0 RXD I O 1 ASCL Open Drain ADC DDC SCL General purpose I O RXD 13 8 7 ASDA P3 1 TXD I O 1 ASDA Open Drain ADC DDC SDA General purpose I O TXD 14 9 8 P3 2 INT0 I O 1 P3 2 Standard 8051 General purpose I O External interrupt 0 15...

Page 8: ... 1 P6 6 Push Pull General purpose I O Clock out 1 31 27 25 P6 7 I O Up 1 Push Pull General purpose I O 32 28 26 VSYNC I Down 0 Input VSYNC input 36 33 30 P1 7 I O 1 Standard 8051 Push Pull General purpose I O 37 34 31 P1 6 I O 1 Standard 8051 Push Pull General purpose I O 38 35 32 P1 5 I O 1 Standard 8051 Push Pull General purpose I O 39 36 33 P1 4 I O 1 Standard 8051 Push Pull General purpose I O...

Page 9: ... memory access The only way to reduce the speed of program memory ROM access is to use a slower clock 3 Dual Data Pointers The DW8051 employs dual data pointers to accelerate data memory block moves The standard 8051 data pointer DPTR is a 16 bit value used to address external data RAM or peripherals The DW8051 maintains the standard data pointer as DPTR0 at SFR locations 82h and 83h It is not nec...

Page 10: ... l 256 bytes of general purpose RAM l 32k bytes of flash for EDID data and other parameters External Program memory l 64k bytes of flash for program memory l The program content can not be read out unless user mass erase the flash first flash 0 64K Internal RAM Direct Indirect addressing flash 64 96K Unused General Purpose RAM DDC_RAM1 2 Unused XFR 0000 7FFF F800 F8FF F900 F9FF FF00 FFFF Internal ...

Page 11: ...ur of these are generated automatically by internal operation timer 0 timer 1 timer 2 and the serial port interrupt The other two interrupts are triggered by external pins INT0 and INT1 Moreover the DDC and IIC interrupts are connected to DW8051 1 INT source as the following figure A_WR_I AWRI_EN D_WR_I DWRI_EN 128VS_I VSI_EN STOP_I STOPI_EN D_OUT_I DOLI_EN D_IN_I DILI_EN SUB_I SUBI_EN SLV_I SLVI_...

Page 12: ...ransition on the P1 1 pin if enabled by EXEN2 1 3 Baud rate generator Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial Port 0 in serial mode 1 or 3 In baud rate generator mode Timer 2 functions in auto reload mode However instead of setting the TF2 flag the counter overflow generates a shift clock for the serial port function As in normal auto reload mode the o...

Page 13: ...3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 FF B3 IP 1 0 PT2 PS0 PT1 PX1 PT0 PX0 80 B8 T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 00 C8 RCAP2L 00 CA RCAP2H 00 CB TL2 00 CC TH2 00 CD PSW CY AC F0 RS1 RS0 OV F1 P 00 D0 ACC 00 E0 B 00 F0 External Special Function Registers XFR Pin Share Register Pin_share0 0xFF00 Name Bits Read Write Reset State Comments Reserved 7 0 Reserved IIC2E 6 R W 1 0 Pin P5 6 ...

Page 14: ...Pin P3 3 INT1 is used as GPIO this bit must be 0 CLKO2E 1 R W 0 0 Pin P7 6 CLKO2 is P7 6 1 Pin P7 6 CLKO2 is CLKO2 IIC1E 0 R W 1 0 Pin ASCL P3 0 Rxd is P3 0 RXD Pin ASDA P3 1 Txd is P3 1 TXD 1 Pin ASCL P3 0 Rxd is ASCL Pin ASDA P3 1 Txd is ASDA Register Pin_share2 0xFF02 Name Bits Read Write Reset State Comments Reserved 7 5 0 Reserved CLKO1E 4 R W 0 0 Pin P6 6 CLKO1 is P6 6 1 Pin P6 6 CLKO1 is CL...

Page 15: ... W 0 0 P5 1 is input pin 1 P5 1 is output pin P50OE 0 R W 0 0 P5 0 is input pin 1 P5 0 is output pin Register Port6_output_enable 0xFF04 Name Bits Read Write Reset State Comments P67OE 7 R W 0 0 P6 7 is input pin 1 P6 7 is output pin P66OE 6 R W 0 0 P6 6 is input pin 1 P6 6 is output pin P65OE 5 R W 0 0 P6 5 is input pin 1 P6 5 is output pin P64OE 4 R W 0 0 P6 4 is input pin 1 P6 4 is output pin P...

Page 16: ... 3 R W 0 0 P1 3 is standar 8051 I O 1 P1 3 is Push Pull output P12_PPO 2 R W 0 0 P1 2 is standar 8051 I O 1 P1 2 is Push Pull output P11_PPO 1 R W 0 0 P1 1 is standar 8051 I O 1 P1 1 is Push Pull output P10_PPO 0 R W 0 0 P1 0 is standar 8051 I O 1 P1 0 is Push Pull output Register Port50_pin_reg 0xFF50 Name Bits Read Write Reset State Comments Reserved 7 1 0 Reserved P50 0 R W 1 Input output value...

Page 17: ..._pin_reg 0xFF55 Name Bits Read Write Reset State Comments Reserved 7 1 0 Reserved P55 0 R W 1 Input output value of P5 5 Register Port56_pin_reg 0xFF56 Name Bits Read Write Reset State Comments Reserved 7 1 0 Reserved P56 0 R W 1 Input output value of P5 6 Register Port57_pin_reg 0xFF57 Name Bits Read Write Reset State Comments Reserved 7 1 0 Reserved P57 0 R W 1 Input output value of P5 7 Registe...

Page 18: ..._pin_reg 0xFF5B Name Bits Read Write Reset State Comments Reserved 7 1 0 Reserved P63 0 R W 1 Input output value of P6 3 Register Port64_pin_reg 0xFF5C Name Bits Read Write Reset State Comments Reserved 7 1 0 Reserved P64 0 R W 1 Input output value of P6 4 Register Port65_pin_reg 0xFF5D Name Bits Read Write Reset State Comments Reserved 7 1 0 Reserved P65 0 R W 1 Input output value of P6 5 Registe...

Page 19: ...ister Port77_pin_reg 0xFF61 Name Bits Read Write Reset State Comments Reserved 7 1 0 Reserved P77 0 R W 1 Input output value of P7 7 Low Voltage Reset Power on Reset When the voltage level of power supply is below VLT the low voltage reset LVR generates a chip reset signal After the power supply is above VUT 2 6V LVR remain in reset state for 65536 X tal cycle tPOR to guarantee the chip exit reset...

Page 20: ...the conversion will be complete in less than 12 us for 4 channels Register ADC_control 0xFF0B Name Bits Read Write Reset State Comments STRT_ADC 7 R W 0 Write 1 to start the A D conversion Auto clear when A D Conversion has been completed 0 A D Conversion has been completed 1 A D Conversion is not completed yet ADC_TEST 6 R W 0 0 Normal operation 1 ADC test mode reserved 5 3 R W 0 Reserved BIAS_AD...

Page 21: ... whole chip operate at higher or lower speed for different demands After reset RTD2120 uses crystal frequency as the system clock User can program the PLL to operate at the desired frequency and select system clock to PLL output by setting MCU_CLK_SEL RTD2120 will switch system clock to PLL output only when PLL is stable Moreover the divider is glitch free so user can modify its value at any time ...

Page 22: ...set PWDN_PLL 0 R W 1 0 normal operation 1 power down PLL Register PLL_filter_control 0xFF11 Name Bits Read Write Reset State Comments reserved 7 4 0 VR 3 2 R W 0 Loop filter resister 00 16 32k 01 19 12k 10 21 92k 11 24 72k PLL_IP 1 0 R W 2 Charge Pump current Ich 5u bit 1 10u bit 0 5u Register PLL_M_N_DIV 0xFF12 Name Bits Read Write Reset State Comments M_CODE 7 4 R W 1 Actual M M_CODE 1 N_CODE 3 ...

Page 23: ...d Both DDC slaves are in DDC1 mode after reset When a high to low transition is detected on ASCL DSCL pin the DDC slave will enter DDC2 transition mode The DDC slave can revert to DDC1 mode if the SCL signal keeps unchanged for 128 VSYNC periods in DDC2 transition mode and RVT_A_DDC1_EN RVT_D_DDC1_EN 1 In DDC2 transition mode the DDC slave will lock in DDC2 mode if a valid control byte is received...

Page 24: ...al clock 1 PLL clock A_DDC2 2 R W 0 Force to ADC DDC to DDC2 mode 0 Normal operation 1 DDC2 is active RST_A_DDC 1 R W 0 Reset ADC DDC circuit 0 Normal operation 1 reset auto cleared RVT_A_DDC 1_EN 0 R W 0 ADC DDC revert to DDC1 enable SCL idle for 128 VSYNC 0 Disable 1 Enable Register DVI_DDC_enable 0xFF23 Name Bits Read Write Reset State Comments D_DDC_ADD R 7 5 R W 0 DVI DDC Channel Address Leas...

Page 25: ... clock 0 crystal clock 1 PLL clock D_DDC2 2 R W 0 Force to DVI DDC to DDC2 mode 0 Normal operation 1 DDC2 is active RST_D_DDC 1 R W 0 Reset DVI DDC circuit 0 Normal operation 1 reset auto cleared RVT_D_DDC 1_EN 0 R W 0 DVI DDC revert to DDC1 enable SCL idle for 128 VSYNC 0 Disable 1 Enable Register DDCRAM_partition 0xFF26 Name Bits Read Write Reset State Comments reserved 7 3 00 Reserved VS_CON 2 ...

Page 26: ...egister IIC_status 0xFF2B Name Bits Read Write Reset State Comments A_WR_I 7 R W 0 If ADC DDC detects a STOP condition in write mode this bit is set to 1 Write 0 to clear D_WR_I 6 R W 0 If DVI DDC detects a STOP condition in write mode this bit is set to 1 Write 0 to clear 128VS_I 5 R W 0 In DDC2 Transition mode SCL idle for 128 VSYNC Write 0 to clear STOP_I 4 R W 0 If IIC detects a STOP condition...

Page 27: ...ce DOI_EN 3 R W 0 0 Disable the D_OUT_I signal as an interrupt source 1 Enable the D_OUT_I signal as an interrupt source DII_EN 2 R W 0 0 Disable the D_IN_I signal as an interrupt source 1 Enable the D_IN_I signal as an interrupt source SUBI_EN 1 R W 0 0 Disable the SUB_I signal as an interrupt source 1 Enable the SUB_I signal as an interrupt source SLVI_EN 0 R W 0 0 Disable the SLV_I signal as an...

Page 28: ... second stage output PWM2_CK 4 R W 0 0 Select first stage output 1 Select second stage output PWM_CK_SE L 3 R W 0 PWM clock generator input source 0 Crystal 1 PLL output reserved 2 0 Reserved PWM_M 1 0 R W 0 PWM clock first stage divider Register PWM_divider_N 0xFF31 Name Bits Read Write Reset State Comments PWM_N 7 0 R W 0 PWM clock Second stage divider Register PWM0_duty_width 0xFF32 Name Bits R...

Page 29: ...e as PWM0 01 PWM3 is the same as PWM1 1x PWM3 is the same as PWM2 Watchdog Timer The Watchdog Timer automatically generates a device reset when it is overflowed The interval of overflow is about 0 25 sec to 2 sec assume crystal is 12MHz and can be programmed via register CNT1 CNT1 N EN_WDT BY_CNT3 WDT reset OSC 0 0 1 1 CNT3 3 210 CNT2 210 BY_CNT2 Register WATCHDOG_timer 0xFF36 Name Bits Read Write...

Page 30: ...flash program speed Register ISP_slave_address 0xFF37 Name Bits Read Write Reset State Comments ISP_ADDR 7 2 R W 25 ISP slave address ISP_ADDR_I NC_A 1 R 1 Received LSB of ISP slave address of ADC DDC channel 0 address is nonincrease 1 address is auto increase ISP_ADDR_I NC_D 0 R 1 Received LSB of ISP slave address of DVI DDC channel 0 address is nonincrease 1 address is auto increase Register opt...

Page 31: ...rite 1 to start page erase Register RAM_test 0xFF3A Name Bits Read Write Reset State Comments reserved 7 4 0 Reserved EXT_RAM_B IST 3 R W 0 Start BIST function for MCU external RAM 512 bytes 0 finished and clear 1 start EXT_RAM_S TA 2 R 0 Test result about MCU external RAM 0 fail 1 ok INT_RAM_BI ST 1 R W 0 Start BIST function for MCU internal RAM 256 bytes 0 finished and clear 1 start INT_RAM_S TA...

Page 32: ...L ADC0_convert_res ult FF0C ADC0_CONV_DATA ADC1_convert_res ult FF0D ADC1_CONV_DATA ADC2_convert_res ult FF0E ADC2_CONV_DATA ADC3_convert_res ult FF0F ADC3_CONV_DATA PLL_control FF10 PLL_STA DVSET WD_RST WD_SET PWDN_P LL PLL_filter_control FF11 VR PLL_IP PLL_M_N_DIV FF12 M_CODE N_CODE DIV Regulator_control FF13 VBG V_SEL ADC_DDC_enable FF20 A_DDC_ADDR A_DDC_ W_STA A_DDCR AM_W_E N A_DBN_E N A_DDC_E...

Page 33: ...M1_C K PWM2_C K PWM_CK _SEL PWM_M PWM_divider_N FF31 PWM_N PWM0_duty_width FF32 PWM0_DUT PWM1_duty_width FF33 PWM1_DUT PWM2_duty_width FF34 PWM2_DUT PWM_source_sele ct FF35 PWM5_SEL PWM4_SEL PWM3_SEL WATCHDOG_tim er FF36 WDT_EN CLR_WD T BY_CNT2 BY_CNT3 CNT1 ISP_slave_address FF37 ISP_ADDR ISP_ADD R_INC_A ISP_ADD R_INC_D option FF38 PORT_PI N_REG MCU_CL K_SEL CKOUT_ SEL Flash_page_erase_ control FF...

Page 34: ... 2 DC Characteristics Operating Condition 0 TA 70 VDD 3 3V 0 3V PARAMETER SYMBOL MIN TYP MAX UNITS Supply Voltage VDD 3 0 3 3 3 6 V Supply Current IVDD 22 1 31 2 mA Supply Current Power Saving IVDD mA Output High Voltage VOH 2 4 VDD V Output Low Voltage VOL GND 0 5 V Input High Voltage VIH 2 0 V Input Low Voltage VIL 0 8 V I O Pull up resistance RPU 100 300 Ω I O Pull down resistance RPD 50 150 Ω ...

Page 35: ...OOTPRINT 2 0mm A2 1 35 1 40 1 45 0 053 0 055 0 057 LEADFRAME MATERIAL c 0 09 0 20 0 004 0 008 DOC NO D 9 00 BSC 0 354 BSC APPROVE VERSION 02 D1 7 00 BSC 0 276 BSC DWG NO PKGC 065 D2 5 50 0 217 CHECK DATE E 9 00 BSC 0 354 BSC REALTEK SEMICONDUCTOR CORP E1 7 00BSC 0 276 BSC E2 5 50 0 217 b 0 17 0 20 0 27 0 007 0 008 0 011 e 0 50 BSC 0 0196 BSC TH 0o 3 5o 7o 0o 3 5o 7o L 0 45 0 60 0 75 0 018 0 0236 0...

Page 36: ...014 0 15 0 25 0 36 4 General appearance spec should be based D 0 646 0 653 0 660 16 41 16 59 16 74 on final visual inspection spec E 0 646 0 653 0 660 16 41 16 59 16 74 TITLE 44L PLCC 0 653 X 0 653 e 0 05 BSC 1 27 BSC PACKAGE OUTLINE DRAWING GD 0 590 0 610 0 630 14 98 15 49 16 00 LEADFRAME MATERIAL GE 0 590 0 610 0 630 14 98 15 49 16 00 APPROVE DOC NO 510 ASS P004 HD 0 675 0 690 0 715 17 15 17 53 ...

Page 37: ...formation The available RTD2120 related products are listed below Part No Flash Size Package Type RTD2120K 96K byte 44 QFP RTD2120L 96K byte 48 LQFP RTD2120S 96K byte 44 PLCC RTD2120L LF 96K byte 48 LQFP lead free RTD2120S LF 96K byte 44 PLCC lead free ...

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