Realtek RTD2120K, Manual

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Realtek RTD2120-series
confidential 23
Register::regulator_control 0xFF13
Name Bits Read/Write Reset State Comments
reserved 7:5 -- 0
VBG 4:3 R/W 1 bandgap voltage select
00: 1.14v
01: 1.20v
10: 1.27v
11: 1.34v
V_SEL 2:0 R/W 4 Regulator 1.8v voltage select
000: 2.22
001: 2.12
010: 2.0
011: 1.9
100: 1.8
101: 1.7
110: 1.6
111: 1.5
DDC
RTD2120 has two DDC ports for both D-sub and DVI interface. The external master can access
DDC_RAM1(F900~F97F) through pin ASDL and ASDA by ADC DDC channel or DDC_RAM2
(F980~F9FF) through pin DSDL and DSDA by DVI DDC channel. Besides, the DDC_RAM1 and
DDC_RAM2 can be combined together to form a 256-bytes DDC_RAM for just ADC/DVI DDC
slave by setting DDCRAM_SIZ (FF26[1:0]).
The DDC of RTD2120 is compliant with VESA DDC standard. Both DDC slaves are in DDC1
mode after reset. When a high to low transition is detected on ASCL/DSCL pin, the DDC slave will
enter DDC2 transition mode. The DDC slave can revert to DDC1 mode if the SCL signal keeps
unchanged for 128 VSYNC periods in DDC2 transition mode and RVT_A_DDC1_EN /
RVT_D_DDC1_EN = 1. In DDC2 transition mode, the DDC slave will lock in DDC2 mode if a valid
control byte is received. Furthermore, user can force the DDC slave to operate DDC2 mode by setting
A_DDC2 / D_DDC2 = 1.
(Refers to the VESA
“
Display Data Channel Standard
”
for detailed)
Register::ADC_DDC_enable 0xFF20
Name Bits Read/Write Reset State Comments
A_DDC_ADD
R 7:5 R/W 0 ADC DDC Channel Address Least
Significant 3 Bits
(The default DDC channel address MSB 4
Bits is
“
A
”
)
reserved 4 -- 0 Reserved
A_DDC_W_S
TA 3 R/W 0 ADC DDC Write Status (for external DDC
access only)
It is cleared after write.
A_DDCRAM
_W_EN 2 R/W 0 ADC DDC SRAM Write Enable (for
external DDC access only)