RCA 301, Programmer'S Reference Manual

Page: 63 / 235

+ Add (ADD)
Repeatable
General Description
This instruction performs decimal addition in accordance with algebraic rules, providing a non-zero suppressed
sum, which is stored in the memory location originally occupied by the augend. The two operands must be equal in
length, but may be of any length up to forty-four characters per each operand.
Format
Operation — T
N —Number of characters (0-44) in each operand. (See Appendix F-I.)
A Address — HSM location of least significant digit of augend and sum.
B Address — HSM location of least significant digit of addend.
Direction of Operation
Right to left.
Outline of Operation
This instruction operates in the following cycle:
The contents of the N Register are examined. If zero, the instruction terminates. If other than zero, the contents
of the HSM location specified by the A Register are transferred to the D
2
portion of the D Register; the contents
of the HSM location specified by the B Register are transferred to the D
3
portion of the D Register. The contents of
the D Register are used to generate an address in the Sum or Difference Table located in HSM depending on the
sign in each operand. If the signs of the operands are alike, the Sum Table is addressed; if unlike, the Difference
Table is addressed. The character thus addressed is transferred to the HSM location specified by the A Register.
The contents of the A, B, and N Registers are decremented by one and the cycle is repeated.
The sign of each operand does not require a separate character location, but is indicated by the 2
1
bit of the
least significant digit (LSD) of each operand. When a one bit is present in the 2
5
position, the sign is negative.
Otherwise it is assumed positive.
In the event there is a carry beyond the most significant digit (MSD) of the sum, a one bit is placed in the 2'
bit position of the MSD of the sum and the first Overflow Indicator, which is present in all Processors, is set. In a
Processor with a 40,000 character memory there may be an additional overflow carry from the 2
J
to the 2' position
of the MSD of the sum and a second Overflow Indicator set. The 2
4
and 2
:>
bit positions of the MSD of the sum then
act as a two bit binary counter. Each Overflow Indicator can be sensed by the Conditional Transfer of Control
instruction.
When there is a carry beyond the MSD of the sum, and the first Overflow Indicator has already been set in a
Computer containing only one Overflow Indicator, the Computer stops on an alarm. When there is a carry beyond
the MSD of the sum in a Computer with a second Overflow Indicator and this indicator has already been set, the
Computer stops on an alarm.
The only allowable one zone bits in the operands of an addition for a processor with up to 20,000 characters
are in the 2
J
bit position of the MSD and the 2
1
and 2
s
positions in the LSD. The only allowable one zone bits in
the operands of an addition for a processor with 40,000 characters are the 2
4
and 2
5
bit positions in the MSD and
the LSD.
In single character operands, however, a one bit in the 2
J
position of either operand causes an alarm stop on the
40,000 character processor.
If the operands have unlike signs and the larger, in absolute value, is the addend, then this causes the "end
around condition" when N equals zero. By the use of the Difference Table, the sum is complemented to give the
correct result.
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