APPENDIX C. SUMMARY
Op.
Code
Instruction
N
A Address
B Address
9
R
Repeat
Number (0-14) of times
to repeat next instruction
in sequence
A = 0000 — do not
staticize when
repeating instruc
tion
A = 0001 — staticize
when repeating
instruction
B
= 0000 — do not staticize when re
peating instruction
B
= 0001 — staticize when repeating in
struction
s
Input/Output Sense
Indicates the input/output
device to be sensed
A,, Aa, Aa
= Must be
zero's (000)
A
0
= specifies tests to be
performed
HSM address of the next instruction to
be executed if the condition(s) being
tested are present
s
Input/Output Sense
(DXC only)
Selects the Unit
H
— (first unit)
I — (second unit)
Ao =
1,
has the other
computer staticized
an
IOS (A«
= 1)
Ai, A
2
= Must be
zeros (00)
Aa = 1
HSM address of the next instruction to
be executed if the condition being tested
is present
s
Automatic
Rollback Control
Selects the device
A« = Must be zero (0)
Ai = 4, allow hardware
rollback
Ai = 8, don't allow
hardware rollback
Aa, Aa
= Must be
zeros (00)
B = Must be zeros (0000)
A
s
Sense Read Error
(Function 1)
M
Ao, Ai, Aa
= Must be
zeros (000)
A3 = 1 Set Read Error
Sense Enhancement
OFF
A
3
= 2 Set Read Error
Sense Enhancement
ON
Must be zeros (0000)
(Function 2)
M = first Control
(318)
S = second Control
(319)
A., Aa, Aa
= Must be
zeros (000)
Ao
= 4 sense for read
parity error
HSM address of the next instruction to
be executed if the condition being tested
is present
T
Logical "AND"
Number
(0-44)
of char
acters in each operand
HSM address of LSD in
first operand (and result)
HSM address of LSD in second operand
u
Exclusive "OR"
Number
(0-44)
of char
acters in each operand
HSM address of LSD in
first operand (and result)
HSM address of LSD in second operand
V
Store Register
Specifies Register to be
stored:
N = 0 — None
N = 1 — P Register
N = 2 — A Register
N = 4 — B Register
N = 8 — S Register
N = & — U Register
HSM address of right
most diad to receive
contents of register,
excluding A Register,
specified by N. If A is
stored, contents of A
Register of previous
instruction are stored in
STA. The contents of A
of this instruction are
ignored
HSM address of next instruction if P
Register is stored. Otherwise,
B
address
is zero
•
C-7
Summary of Contents for 301
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