When the least significant character of an address has zone bits 01, thus forming one of the following
characters:
& for 0
E for 5
A for 1
F for 6
B for 2
G for 7
C for 3
H for 8
D for 4
I for 9
the address is an indirect address. When an indirect address is staticized, the contents of the HSM location addressed
by that indirect address replace it in the register. If the replacing address is also an indirect address, it too will be
replaced in the register by the contents of the memory locations it addresses. The initial register Settings for any
instruction, are therefore, not established until both the A and B Registers have been supplied with direct addresses.
An indirect address must address the least significant diad of another address. Indirect addressing has proven
valuable in reducing programmer effort, processing time, and instruction storage. Each indirect address requires
two additional status levels (14 microseconds).
PROGRAM CONTROL
Program Control is the control unit of the system. It interprets and executes the instructions stored in the High
Speed Memory, directs the sequence of operations within the system, controls operation of the input/output devices,
and performs automatic accuracy checks.
Program Control includes a number of specialized devices. Those which are of interest to the programmer are
diagrammed in Figure 5, and are briefly discussed below, along with certain automatic Program Control functions.
Registers
The
Memory Addressing Register
stores the address of the HSM location to be processed. The capacity of this
register is four RCA 301 characters.
The
Memory Register
has a capacity of two RCA 301 characters. It receives the diad contents that emerge from
or are to be placed in the HSM. A series of Memory Output Gates permit or inhibit entrance into the Memory Register
of either or both of the characters that emerge from the HSM.
The
Interchange
links the Memory Register with the Memory Address Bus. It selects the proper bus or busses
to which characters are transferred from the Memory Register according to the operation being performed. For
example, during staticizing operations, it selects the proper busses for the transfer of two instruction characters
(diad) at a time into the proper registers. During an input-output operation, it selects the correct bus for single
character transfer of information into and out of the HSM.
The
A Register
has a capacity of four RCA 301 characters. It receives the A address of an instruction, and when
necessary, holds the address of each character being processed in the Normal Mode.
The
B Register
has a capacity of four RCA 301 characters. It receives the B address of an instruction, and when
necessary, holds the address of each character being processed in the Normal Mode.
The P
Register
has a capacity of four characters and holds the HSM address of the next instruction in sequence.
The
NOR (Normal Operation) Register
has a capacity of one RCA 301 character. It holds the Operation Code
of the instruction currently being executed in the Normal Mode.
The N
Register
has a capacity of one character. It holds the N character of the currently processed instruction.
The
N
b
(Repeat) Register
is used by the Repeat instruction to store the count.
When an operation is executed in the Simultaneous Mode, four Registers are utilized:
Simultaneous Operation Register (SOR) (receives OP Code)
M Register (receives N character)
S Register (receives A address)
T Register (receives B address)
III-3
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