Rastergraf Topaz, User Manual

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Rastergraf
Programming On-board Devices and Memories 5-23
Figure 5-4 THC63DV164 RGB to 24-bit TMDS Mapping Diagram
Notes: In 24 bit Single Clock Dual Edge mode, the THC63DV164 will look at the first clock edge (either falling or rising)
after DE goes high to determine the first pixel data. EDGE pin has no affect in 24 bit Single Clock Dual Edge mode.
Notes:
1
In this figure, clock edges represented by arrows signify latching edge.
2
Color pixel components are represented as R:Red, G:Green and B:Blue.
3
Bit significance with in a color: [7:0] = [MSB:LSB]
24bit Mode Data Mapping Table
P0 P1 Pn
D23 R0[7] R1[7] Rn[7]
D22 R0[6] R1[6] Rn[6]
D21 R0[5] R1[5] Rn[5]
D20 R0[4] R1[4] Rn[4]
D19 R0[3] R1[3] Rn[3]
D18 R0[2] R1[2] Rn[2]
D17 R0[1] R1[1] Rn[1]
D16 R0[0] R1[0] Rn[0]
D15 G0[7] G1[7] Gn[7]
D14 G0[6] G1[6] Gn[6]
D13 G0[5] G1[5] Gn[5]
D12 G0[4] G1[4] Gn[4]
D11 G0[3] G1[3] Gn[3]
D10 G0[2] G1[2] Gn[2]
D9 G0[1] G1[1] Gn[1]
D8 G0[0] G1[0] Gn[0]
D7 B0[7] B1[7] Bn[7]
D6 B0[6] B1[6] Bn[6]
D5 B0[5] B1[5] Bn[5]
D4 B0[4] B1[4] Bn[4]
D3 B0[3] B1[3] Bn[3]
D2 B0[2] B1[2] Bn[2]
D1 B0[1] B1[1] Bn[1]
D0 B0[0] B1[0] Bn[0]
DE
D[23:0]
IDCLK+
IDCLK+
IDCLK+
P
0
P
1
P
n-1
P
n
DSEL=High
24bit mode (BSEL=High) clock edge settings
First Latch edge
DSEL=Low, EDGE=Low
DSEL=Low, EDGE=High