Rastergraf Topaz, User Manual

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Rastergraf
General Information 1-21
way, each LVDS block can drive one SXGA+ panel (1400x1050x24
@60Hz). The LVDS1 Interface is hardwired to Panel Controller
(Primary). It can be programmed to drive 18 or 24 bpp panels, and, if used
in conjunction with the LVDS2 Interface, it can be used to drive a two
channel, two pixels per clock panel of up to QXGA size (2048x1536).
Figure 1-15 LVDS Flat Panel Output Block Diagram
TFT LVDS Panel
T xOut0 +
-
T xOut1 +
-
T xOut2 +
-
T xC LKOu +
-
R xln0 +
-
R xln1 +
-
R xln2 +
-
-
RxOut
RxOut
RxOut
RxOut
RxOut
RxOut
RxCLKOu
R [7:0]
G[7:0]
B[7:0]
HYSNC
VSYNC
DE
FPSC
1
LVDS
clock
4
Data
Pairs
T xOut3 +
-
R xln3 +
-