5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 18 / 77
(I)(0/1.8 V)
module is turned off.
When it is at high level, the
module is turned on.
100k
Ω resistor
7
USB_D+
USB_DP
AI,
AO
USB 2.0 differential data (+)
8
W_DISABLE1#
(I)(0/1.8 V)
W_DISABLE1#
DI
Airplane mode control.
Active LOW.
1.8/3.3 V power
domain
9
USB_D-
USB_DM
AI,
AO
USB 2.0 differential data (-)
10
GPIO_9/LED_1#
(OD)(0/3.3 V)
WWAN_LED#
OD
RF status indication LED
It is an open
drain and active
LOW signal.
11
GND
GND
Ground
12
Key
Notch
Notch
13
Key
Notch
Notch
14
Key
Notch
Notch
15
Key
Notch
Notch
16
Key
Notch
Notch
17
Key
Notch
Notch
18
Key
Notch
Notch
19
Key
Notch
Notch
20
GPIO_5
/AUDIO_0
PCM_CLK
IO
PCM data bit clock
1.8 V power
domain
21
CONFIG_0
CONFIG_0
DO
Not connected internally
22
GPIO_6
/AUDIO_1
PCM_DIN
DI
PCM data input
1.8 V power
domain
23
GPIO_11
/WOWWAN#
WAKE_ON_WAN#
OD
Wake up the host.
Active LOW.
Open drain
24
GPIO_7
/AUDIO_2
PCM_DOUT
DO
PCM data output
1.8 V power
domain
25
DPR
(I)(0/1.8 V)
DPR
DI
Dynamic power reduction.
High level by default.
1.8 V power
domain
26
GPIO_10
/W_DISABLE2#
W_DISABLE2#
DI
GNSS disable control.
Active LOW.
1.8/3.3 V power
domain
27
GND
GND
Ground