5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 29 / 77
Host
Module
RESET_N
Reset
Logic
GPIO
67
VDD 1.8V
Reset pulse
200-700 ms
R1
100k
R5
100k
R4
10R
Q2
NMOS
Figure 14: Reference Circuit of RESET_N with NMOS Driving Circuit
Module
RESET_N
Reset
Logic
67
VDD 1.8V
200-700ms
S1
TVS
R1
100k
33pF
C1
Note:
The capacitor C1 is recommended to be less than 47pF.
Figure 15: Reference Circuit of RESET_N with Button
The reset scenario is illustrated in the following figure.
V
IL
0.5V
VCC
200ms
Resetting
Module Status
Running
RESET_N
Restart
700ms
Figure 16: Resetting Timing of the Module