Power Application Controller
®
-28-
Copyright 2020 © Qorvo, Inc.
Rev 1.2
– Jan 17, 2019
The BEMF POS sample and hold circuits are toggled based on the POS bit in the EMUX packet
with the falling edge of the 1
st
clock cycle.
The AIO10, AIO32 and AIO54 sample and hold circuits are toggled based on the HLD<2:0> bits
with the falling edge of the 4
th
clock cycle.
The AFE MUX select is switched with the falling edge of the 8
th
clock based on the data of bits
3:0 of the EMUX packet.
Figure 7-1 EMUX Timing Diagram
EMUXC
EMUXD
POS
HDL2
HDL1
HDL0
MUX3
MUX2
MUX1
MUX0
POS S/H
DAOxy S/H
MUXA
