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Power Application Controller

®

-18-

Copyright 2020 © Qorvo, Inc.

Rev 1.2

– Jan 17, 2019

5

PAC5527 IO

5.1

Overview

The Digital Peripheral MUX (DPM) on the PAC55XX family allows flexible assignment of
peripheral functions to IO pins.

Each member of the family has a different set of IO pins that are available. It is important during
application design that the designer consider the available IO pins to make sure the necessary
peripherals will be available.

Below is a diagram of the GPIO and MUX structure.

Figure 5-1 GPIO and DPM Block Diagram

Each IO can be configured to select 1 of up to 8 digital peripheral signals. Some IOs also may
be used as an ADC input. For information on how to configure the IO for each of these
situations, see the PAC55XX Family User Guide.

The PAC5527 has the following IO pins available for application use:

▪

PA[7:0]

– Reserved for MMPM, ASPD, CAFE

▪

PB[7:0]

– Reserved for ASPD

▪

PD[7:4]

▪

PE[3:0]

▪

PF[7:0]

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Summary of Contents for PAC5527

Page 1: ...1 Copyright 2020 Qorvo Inc Rev 1 2 Jan 17 2019 PAC5527 Device User Guide Power Application Controller Multi Mode Power ManagerTM Configurable Analog Front EndTM Application Specific Power DriversTM Ar...

Page 2: ...2 Functional Description 14 4 3 USART Configuration 15 4 4 Protocol 15 4 5 Write Register Example 15 4 6 Read Register Example 17 5 PAC5527 IO 18 5 1 Overview 18 5 2 ADC Channels 19 5 3 Digital Perip...

Page 3: ...9 1 Overview 41 9 2 Features 41 9 3 System Block Diagram 42 9 4 Enabling the CAFE 43 9 5 Entering Hibernate Mode 43 9 6 Hibernate wake up using Wake Up Timer 43 9 7 Hibernate wake up using Push Button...

Page 4: ...on 55 9 15 AIO6 57 9 15 1 System Block Diagram 58 9 15 2 AIO6 Digital I O Mode 59 9 15 3 AIO6 Amplifier Mode 59 9 15 4 AIO6 Comparator Mode 59 9 15 5 AIO6 Special Mode 60 9 16 AIO7 61 9 16 1 System Bl...

Page 5: ...CFGAIO4 83 9 20 6 SOC CFGAIO5 84 9 20 7 SOC CFGAIO6 85 9 20 8 SOC CFGAIO7 86 9 20 9 SOC CFGAIO8 87 9 20 10 SOC CFGAIO9 88 9 20 11 SOC SIGSET 89 9 20 12 SOC HPDACH 90 9 20 13 SOC HPDACL 90 9 20 14 SOC...

Page 6: ...ing the ASPD 111 10 7 Gate Driver Safe State 111 10 8 Driver Protection 111 10 9 Cycle by Cycle Current Limit 112 10 10 Gate Driver Short Protection 114 10 11 VP UVLO Configuration 114 10 12 Break bef...

Page 7: ...Power Application Controller 7 Copyright 2020 Qorvo Inc Rev 1 2 Jan 17 2019...

Page 8: ...anager System Block Diagram 30 Figure 9 1 CAFE System Block Diagram 42 Figure 9 2 AIO10 Block Diagram 45 Figure 9 3 AIO32 Block Diagram 49 Figure 9 4 AIO54 Block Diagram 53 Figure 9 5 AIO6 System Bloc...

Page 9: ...25 Table 6 3 PAC5527 ADC MUX channels 26 Table 8 1 Power Manager Fault Handling 31 Table 8 2 Power Manager Register Summary 33 Table 9 1 Hibernate Wake Up Timer Options 43 Table 9 2 AIO2 AIO7 Buffer I...

Page 10: ...ting 11h 90 Register 9 13 SOC HPDACL HPDAC Low Setting 12h 90 Register 9 14 SOC LPDACH LPDAC High Setting 13h 90 Register 9 15 SOC LPDAC1 LPDAC Low Setting 14h 90 Register 9 16 SOC SHCFG1 Sample and H...

Page 11: ...ister 10 6 SOC DRVILIMHS High side Driver Current Limit Configuration 7Ah 125 Register 10 7 SOC CFGDRV4 Driver Configuration 4 7Bh 126 Register 10 8 SOC DRV_FLT Driver Fault Flat 7Ch 126 Register 10 9...

Page 12: ...l 2 2 Formatting Styles TYPE EXAMPLE DESCRIPTION Register Name RTCCTL Register names use a capital letter and boldface type Register Bit s RTCCTL RTCCLKDIV Register bits are always represented with th...

Page 13: ...RLx LSGD 3 APPLICATION SPECIFIC POWER DRIVERS CONFIGURABLE ANALOG FRONT END AIO CONTROL 10 DAC 2 PGA CMP 7 DIFF PGA PCMP 3 AMPx CMPx PHCx DAxP PCMPx DAxN ADx AIOx BUF6 PBTN CPH VSS PAC5527 Power Appli...

Page 14: ...O A G The PAC5527 contains two register buses the AHB bus and the APB bus The AHB bus allows the MCU and Debug Port access to FLASH and SRAM via the Memory Controller To access other digital periphera...

Page 15: ...have the following configuration 8 bit mode SCLK active high CPH is sample setup SS active low When communicating with the Analog Peripherals the maximum SCLK frequency is 25MHz 4 4 Protocol The proto...

Page 16: ...Power Application Controller 16 Copyright 2020 Qorvo Inc Rev 1 2 Jan 17 2019 Figure 4 2 Analog Peripheral Register Write Timing...

Page 17: ...e value 56h 2Bh 1 0b for read transaction Write SSPADAT with a dummy character Read last data from MISO from SSPADAT this is the register value The timing diagram from a read operation is shown below...

Page 18: ...er consider the available IO pins to make sure the necessary peripherals will be available Below is a diagram of the GPIO and MUX structure Figure 5 1 GPIO and DPM Block Diagram Each IO can be configu...

Page 19: ...1 2 Jan 17 2019 5 2 ADC Channels The ADC channels that are available on the PAC5527 are shown in the table below Table 5 1 PAC5527 ADC Input Pins ADC Channel IO PIN ADC0 PG71 ADC4 PF4 ADC5 PF5 ADC6 PF...

Page 20: ...B6 TAPWM6 TBPWM6 TCPWM6 TDPWM6 GPIOD P4 GPIOD4 TBPWM4 TCPWM4 TDQEPIDX TBQEPIDX USDSCLK TRACED3 USDMOSI P5 GPIOD5 TBPWM5 TCPWM5 TDQEPPHA TBQEPPHA USDSS CANRXD USDMISO P6 GPIOD6 TBPWM6 TCPWM6 TDQEPPHB T...

Page 21: ...OS MCU PA0 The IRQ1 interrupt is available on the MCU on the PA7 IO To receive this interrupt the MCU must configure PA7 as an edge triggered active low interrupt Error conditions such as power manage...

Page 22: ...t are used for signal sampling are shown in the diagram below Figure 6 1 PAC5527 ADC MUX inputs AFE MUX MCU 12 bit ADC PWRMON MUX VCCIO x 4 10 VCC33 x 4 10 VP x 1 10 VCORE VSYS x 4 10 VREF x 5 10 VPTA...

Page 23: ...d ADC configuration In the PAC5527 there are 4 external pins and one internal ADC channel that may be configured for ADC analog input that are shown in the table below Table 6 1 PAC5527 ADC MUX channe...

Page 24: ...rs or through the EMUX from the MCU s DTSE When the ADC is configured for manual mode the EMUX enable function in the AFE should be disabled To select the AFE MUX channel using the SOC registers set S...

Page 25: ...ial Amplifier for AIO54 AB1 0011b Analog bus AB1 AB2 0100b Analog bus AB2 AB3 0101b Analog bus AB3 AB4 0110b Analog bus AB4 AB5 0111b Analog bus AB5 AB6 1000b Analog bus AB6 AB7 1001b Analog bus AB7 A...

Page 26: ...is on the analog bus channel AB11 which is directly connected to the AFE MUX The channels available on the PWRMON MUX are shown in the table below Table 6 3 PAC5527 ADC MUX channels Channel SOC PWRCT...

Page 27: ...e and hold engine POS BEMF sample and hold engine The format of the EMUX command used to control the AFE MUX is the same as is shown in SOC SHCFG2 The EMUX data is transmitted MSB first BIT NAME DESCR...

Page 28: ...dge of the 1st clock cycle The AIO10 AIO32 and AIO54 sample and hold circuits are toggled based on the HLD 2 0 bits with the falling edge of the 4th clock cycle The AFE MUX select is switched with the...

Page 29: ...linear regulators provide VSYS VCCIO VCC33 VCC18 and VCORE supplies for 5V system 3 3V I O 3 3V mixed signal 1 8V FLASH and 1 2V microcontroller core circuitry The power manager also handles system fu...

Page 30: ...o generate the supply for the integrated high side gate drivers and a Medium Voltage Buck Boost Converter MVBB to generate the supply for the integrated low side gate drivers Five additional linear re...

Page 31: ...able VP VSYS VCCIO VCORE and VCC33 SOC FAULT VPFLT VSYS Disable VSYS VCCIO VCORE and VCC33 SOC FAULT VSYSFLT VCCIO Disable VCCIO VCORE VCC33 SOC FAULT VCCIOFLT SOC FAULT VCOREFLT SOC FAULT VCC33FLT VC...

Page 32: ...ure exceeds the fault threshold of 165 C the SOC FAULT TMPFAULT bit is set to 1b When this fault occurs the PAC5527 is forced into hibernate mode and will stay in hibernate mode until the push button...

Page 33: ...SOC FAULT Fault condition indication register 00h 01h SOC STATUS Hardware status condition register 00h 02h SOC MISC Miscellaneous features register 00h 03h SOC PWRCTL Power Manager control register 0...

Page 34: ...and IRQ1 is asserted Write 1b to clear when not masked 0b No temperature warning 1b Temperature warning 5 TMPFLT R 0x0 Temperature fault status If the temperature reaches the fault threshold this bit...

Page 35: ...No WDT reset 1b WDT Reset 4 RFU R 0x0 Reserved 3 VPLOW R 0x0 Real time VP Low Status When set the VP supply is below the power good threshold 0b No VP low 1b VP low 2 VPLOW_LATCH R W 0x0 Latched VP Lo...

Page 36: ...RFU R 0x0 Reserved 3 MCUALIVE R W 0x0 MCU Alive Set by the MCU to indicate that it is alive Before this bit is set ignore all MCU commands EMUX gate driver except SPI register commands This bit will...

Page 37: ...7 6 RFU R 0x0 Reserved 5 3 PWRMON R W 0x0 Power Monitor Signal This field selects the signal to use for AB11 for ADC monitoring buffered 000b VCORE 001b VP x 1 10 010b VCC33 x 4 10 011b VCCIO x 4 10...

Page 38: ...e Warning Interrupt 0b Not enabled 1b Enabled asserts IRQ1 5 VPFLTINT R W 0x0 VP Fault Interrupt Enabled 0b Not enabled 1b Enabled 4 VSYSFLTINT R W 0x0 VSYS Fault Interrupt Enabled 0b Not enabled 1b E...

Page 39: ...ssue a system soft reset This bit is always read as 0b When set the STATUS SRST bit will be latched to a 1b so the MCU knows the system is being started after a soft reset 0b Do not issue soft reset 1...

Page 40: ...SOC SYSCONF System Configuration 2Bh BIT NAME ACCESS RESET DESCRIPTION 7 3 RFU R 0011 0b Reserved 2 VPSET R W 1b VP Output Voltage Setting 0b 10V 1b 12V default 1 MVBB_ILIM R W 0b MVBB Inductor Curren...

Page 41: ...can function as digital inputs or digital open drain outputs The PAC proprietary configurable analog signal matrix CASM and configurable digital signal matrix CDSM allow real time asynchronous analog...

Page 42: ...LP DAC HP DAC DIFF PGA PCOMP MUX OFFSET CAL PROTECT IRQ1 PR ADC AFE MUX DAxN ADC MUX VTEMP VMON VREF VM CONFIGURABLE ANALOG SIGNAL MATRIX AMPx PGA MUX MUX BUF6 COMPARATOR MUX DINx CONFIGURABLE ANALOG...

Page 43: ...rnate Wake up Timer or the Push button function Before entering hibernate mode one of these two methods must be configured or the PAC5527 will not be able to exit hibernate mode 9 6 Hibernate wake up...

Page 44: ...the IRQ1 interrupt to the MCU To de assert this interrupt set SOC STATUS PBSTAT_LATCHED to 1b If the PAC5527 is in hibernate and AIO6 transitions high for the de bouncing time period the SOC MISC HIB...

Page 45: ...ic Polarity OD CFGAIO0 OPT0 CFGAIO0 MODE10 MUX DINSIG0 DIN0 DOUTSIG0 DOUT0 I O CFGAIO0 MUX0 CFGAIO1 OPT1 CFGAIO0 MODE10 CFGAIO1 POL1 I O Logic Polarity OD MUX DINSIG0 DIN1 DOUTSIG0 DOUT1 I O CFGAIO1 M...

Page 46: ...ty of the signal between AIO1 input output and MUX1 9 12 3 AIO1 AIO0 Differential Amplifier Mode The differential amplifier may be configured as a differential amplifier or as an infinite impedance si...

Page 47: ...ormat of the bits are the same as shown in SOC SHCFG2 9 12 5 AIO1 AIO0 Protection In differential amplifier mode SOC CFGAIO0 MODE10 01b a high side comparator protector HP10 and a low side comparator...

Page 48: ...Rev 1 2 Jan 17 2019 The output of LP10 can also trigger the IRQ1 interrupt by setting SOC PROTINTEN LP10INTEN to 1b The real time status can be observed using SOC SIGINTF LP10STAT and the latched int...

Page 49: ...CFGAIO2 MODE32 AIO2 AIO3 Digital I O CFGAIO2 POL2 I O Logic Polarity OD CFGAIO2 OPT2 CFGAIO2 MODE32 MUX DINSIG0 DIN2 DOUTSIG0 DOUT2 I O CFGAIO2 MUX2 CFGAIO3 OPT3 CFGAIO2 MODE32 CFGAIO3 POL3 I O Logic...

Page 50: ...ty of the signal between AIO3 input output and MUX3 9 13 3 AIO3 AIO2 Differential Amplifier Mode The differential amplifier may be configured as a differential amplifier or as an infinite impedance si...

Page 51: ...ormat of the bits are the same as shown in SOC SHCFG2 9 13 5 AIO3 AIO2 Protection In differential amplifier mode SOC CFGAIO2 MODE32 01b a high side comparator protector HP32 and a low side comparator...

Page 52: ...ther AIO2 or AIO7 in the PAC5527 CAFE To enable this buffer set SOC DOUTSIG1 AIOBUFEN 1b The input signal for this buffer may be selected by using SOC DOUTSIG1 AIOBUFSELIN with the values below Table...

Page 53: ...ic Polarity OD CFGAIO4 OPT4 CFGAIO4 MODE54 MUX DINSIG0 DIN4 DOUTSIG0 DOUT4 I O CFGAIO4 MUX4 CFGAIO5 OPT5 CFGAIO4 MODE54 CFGAIO5 POL5 I O Logic Polarity OD MUX DINSIG0 DIN5 DOUTSIG0 DOUT5 I O CFGAIO5 M...

Page 54: ...ty of the signal between AIO5 input output and MUX5 9 14 3 AIO4 AIO5 Differential Amplifier Mode The differential amplifier may be configured as a differential amplifier or as an infinite impedance si...

Page 55: ...rmat of the bits are the same as shown in SOC SHCFG2 9 14 5 AIO5 AIO4 Protection In differential amplifier mode SOC CFGAIO4 MODE54 01b a high side comparator protector HP54 and a low side comparator p...

Page 56: ...Rev 1 2 Jan 17 2019 The output of LP54 can also trigger the IRQ1 interrupt by setting SOC PROTINTEN LP54INTEN to 1b The real time status can be observed using SOC PROTSTAT LP54STAT and the latched int...

Page 57: ...ht 2020 Qorvo Inc Rev 1 2 Jan 17 2019 9 15 AIO6 AIO6 may be configured as a digital input single ended programmable gain amplifier comparator output from analog ABUS or as a push button input to wake...

Page 58: ...Bx ABUS MUX CFGAIO6 MUX6 CFGAIO6 GAIN6 CMP CFGAIO6 MODE6 AIO6 Comparator DBx DBUS ABUS MUX AB 3 1 DOUTSIG0 VTHREF VTHREF MUX CFGAIO6 POL6 CMP Polarity CFGAIO6 MUX6 CFGAIO6 OPT6 DINSIG1 DIN6 Input SIGI...

Page 59: ...interrupt status can be monitored by reading SOC SIGINTF AIO6INT and cleared by writing SOC SIGINTF AIO6INTF to 1b 9 15 3 AIO6 Amplifier Mode In AIO6 amplifier mode the push button function must be di...

Page 60: ...detect an over current event and to notify the ASPD to disable the gate drivers much like the differential amplifier mode To signal the ASPD upon the comparator output state set SOC CFGIO1 EN_AIO6_OC...

Page 61: ...ication Controller 61 Copyright 2020 Qorvo Inc Rev 1 2 Jan 17 2019 9 16 AIO7 AIO7 may be configured as a digital input output single ended programmable gain amplifier comparator or a BEMF zero cross c...

Page 62: ...POL7 CMP Polarity CFGAIO7 MUX7 CFGAIO7 OPT7 DINSIG1 DIN7 Input SIGINTF AIO7INT SIGINTEN AIO7REINTEN SIGINTEN AIO7FEINTEN BLANKING BLANKMODE SPECCFG0 AIO7HYS SPECCFG0 HYSMODE SPECCFG2 SMUXAIO7 CMP AIO...

Page 63: ...erted on IRQ2 to the MCU The interrupt status can be monitored by reading SOC SIGINTF AIO7INT and cleared by writing SOC SIGINTF AIO7INTF to 1b 9 16 3 AIO7 Amplifier Mode To configure AIO7 for amplifi...

Page 64: ...1b To enable interrupts for high to low transitions on AIO7 set SOC SIGINTEN AIO7FEINTEN to 1b When the edge is detected an interrupt will be asserted on IRQ2 to the MCU The interrupt status can be m...

Page 65: ...motor phase voltages on AIO 9 7 to AB1 with a 100k resistor to create a star point referent to the comparator The AB1 reference may also be configured to come from AIO6 when in amplifier mode When SOC...

Page 66: ...fer may be selected by using SOC DOUTSIG1 AIOBUFSELIN with the values below Table 9 3 AIO2 AIO7 Buffer Input Select SOC DOUTSIG1 AIOBUFSELIN SIGNAL 00b ADC VREF 2 5V or 3 0V as selected by SOC MISC VR...

Page 67: ...Application Controller 67 Copyright 2020 Qorvo Inc Rev 1 2 Jan 17 2019 9 17 AIO8 AIO8 may be configured as a digital input single ended programmable gain amplifier comparator or a BEMF zero cross comp...

Page 68: ...ABUS MUX AB 3 1 DOUTSIG0 VTHREF VTHREF MUX CFGAIO8 POL8 CMP Polarity CFGAIO8 MUX8 CFGAIO8 OPT8 DINSIG1 DIN8 Input SIGINTF AIO8INT SIGINTM AIO8REINTEN SIGINTM AIO8FEINTEN BLANKING BLANKMODE SPECCFG1 AI...

Page 69: ...erted on IRQ2 to the MCU The interrupt status can be monitored by reading SOC SIGINTF AIO8INT and cleared by writing SOC SIGINTF AIO8INTF to 1b 9 17 3 AIO8 Amplifier Mode To configure AIO8 for amplifi...

Page 70: ...1b To enable interrupts for high to low transitions on AIO8 set SOC SIGINTEN AIO8FEINTEN to 1b When the edge is detected an interrupt will be asserted on IRQ2 to the MCU The interrupt status can be m...

Page 71: ...he motor phase voltages on AIO 9 7 to AB1 with a 100k resistor to create a star point referent to the comparator The AB1 reference may also be configured to come from AIO6 when in amplifier mode When...

Page 72: ...Application Controller 72 Copyright 2020 Qorvo Inc Rev 1 2 Jan 17 2019 9 18 AIO9 AIO9 may be configured as a digital input single ended programmable gain amplifier comparator or a BEMF zero cross comp...

Page 73: ...DBUS ABUS MUX AB 3 1 DOUTSIG0 VTHREF VTHREF MUX CFGAIO9 POL9 CMP Polarity CFGAIO9 MUX9 CFGAIO9 OPT9 DINSIG1 DIN9 Input SIGINTF AIO9INT SIGINTM AIO9REINTEN SIGINTM AIO9FEINTEN BLANKING BLANKMODE SPECCF...

Page 74: ...erted on IRQ2 to the MCU The interrupt status can be monitored by reading SOC SIGINTF AIO9INT and cleared by writing SOC SIGINTF AIO9INTF to 1b 9 18 3 AIO9 Amplifier Mode To configure AIO9 for amplifi...

Page 75: ...1b To enable interrupts for high to low transitions on AIO9 set SOC SIGINTEN AIO9FEINTEN to 1b When the edge is detected an interrupt will be asserted on IRQ2 to the MCU The interrupt status can be m...

Page 76: ...he motor phase voltages on AIO 9 7 to AB1 with a 100k resistor to create a star point referent to the comparator The AB1 reference may also be configured to come from AIO6 when in amplifier mode When...

Page 77: ...CFGAIO9 AIO9 Configuration 0x00 0x10 SOC SIGSET Signal manager Configuration 0x00 0x11 SOC HPDACH High Protection Threshold 0x00 0x12 SOC HPDACL High Protection Threshold 0x00 0x13 SOC LPDACH Low Prot...

Page 78: ...ING BEMF Comparator Blanking Configuration 0x00 0x22 SOC SPECCFG0 AIO7 Hysteresis Configuration 0x00 0x23 SOC SPECCFG1 AIO8 AIO9 Hysteresis Configuration 0x00 0x24 SOC SPECCFG2 AIO7 AIO8 Comparator In...

Page 79: ...fier gain setting 000b 1x 010b 1x 011b 2x 001b 4x 100b 8x 101b 16x 110b 16x 111b 16x 3 POL0 RW 0b POL0 AIO0 Polarity If CFGAIO0 OPT0 00b AIO0 input polarity setting If CFGAIO0 OPT0 10b AIO0 output pol...

Page 80: ...b LP10 output to PR disabled 1b LP10 output to PR enabled 3 POL1 RW 0b If CFGAIO1 OPT1 00b AIO1 input polarity setting If CFGAIO1 OPT1 10b AIO1 output polarity setting 0b active high 1b active low OS1...

Page 81: ...ier gain setting 000b 1x 010b 1x 011b 2x 001b 4x 100b 8x 101b 16x 110b 16x 111b 16x 3 POL2 RW 0b If CFGAIO2 OPT2 00b AIO2 input polarity setting If CFGAIO2 OPT2 10b AIO2 output polarity setting 0b act...

Page 82: ...b LP32 output to PR disabled 1b LP32 output to PR enabled 3 POL3 RW 0b If CFGAIO3 OPT3 00b AIO3 input polarity setting If CFGAIO3 OPT3 10b AIO3 output polarity setting 0b active high 1b active low OS3...

Page 83: ...amplifier gain setting 000b 1x 010b 1x 011b 2x 001b 4x 100b 8x 101b 16x 110b 16x 111b 16x 3 POL4 RW 0b If CFGAIO4 OPT4 00b AIO4 input polarity setting If CFGAIO4 OPT4 10b AIO4 output polarity setting...

Page 84: ...b LP54 output to PR disabled 1b LP54 output to PR enabled 3 POL5 RW 0b If CFGAIO5 OPT5 00b AIO5 input polarity setting If CFGAIO5 OPT5 10b AIO5 output polarity setting 0b active high 1b active low OS5...

Page 85: ...THREF 01b AB1 10b AB2 11b AB3 ADMUX 1b Switch ADCIN to AB7 4 SWAP Buffer Swap 0b Do not swap buffer offset 1b Swap buffer offset 3 POL6 AIO6 Polarity Setting 00b active high 01b active low POL6 AIO6 C...

Page 86: ...PT7 AIO7 Comparator Reference select 00b VTHREF 01b AB1 10b AB2 11b AB3 Reserved write as 0b 4 Reserved write as 0b 3 POL7 AIO7 Polarity Setting 00b active high 01b active low POL7 AIO7 Comparator pol...

Page 87: ...11b AB3 OPT8 1 S H bypass for POS 0b Bypass S H for POS signal 1b Do not bypass S H for POS signal 4 OPT8 0 IRQ2 POS output 0b Select IRQ2 POS output POS BEMF 1b Select IRQ2 POS output IRQ2 INT 3 POL...

Page 88: ...ct 00b VTHREF 01b AB1 10b AB2 11b AB3 OPT9 AIO789 comparator output to POS 00b not connected 01b MUX AIO7 comparator output to POS 10b MUX AIO8 comparator output to POS 11b MUX AIO9 comparator output...

Page 89: ...ROTHYS R W 0b HPx Hysteresis 0b Comparator Hysteresis disabled 1b Comparator Hysteresis enabled 2 LPROTHYS R W 0b LPx Hysteresis 0b Comparator Hysteresis disabled 1b Comparator Hysteresis enabled 1 LP...

Page 90: ...tting 13h 9 20 15 SOC LPDACL Register 9 15 SOC LPDAC1 LPDAC Low Setting 14h BIT NAME ACCESS RESET DESCRIPTION 7 0 HPDAC 9 2 R W 0 HPDAC MSB setting bits 9 2 BIT NAME ACCESS RESET DESCRIPTION 7 2 RFU R...

Page 91: ...Enable Note that writing 0b to this field will reset the EMUX state machine 0b disabled 1b enabled 3 ADCBUFEN R W 0b ADCBUF Circuit Enable 0b disabled 1b enabled 2 DAO54SH R W 0b DAO54 Sample and Hol...

Page 92: ...POS value 6 HLD2 R W 0b DAO54 Sample and Hold Output 0b Sample 1b Hold 5 HLD1 R W 0b DAO32 Sample and Hold Output 0b Sample 1b Hold 4 HLD0 R W 0b DAO10 Sample and Hold Output 0b Sample 1b Hold 3 0 MUX...

Page 93: ...54INTEN R W 0b HPROT54 Interrupt enable 0b disabled 1b enabled 5 HP32INTEN R W 0b HPROT32 Interrupt enable 0b disabled 1b enabled 4 HP10INTEN R W 0b HPROT10 Interrupt enable 0b disabled 1b enabled 3 R...

Page 94: ...upt 1b Interrupt write 1 to clear 5 HP32INT R W 0b HPROT32 Interrupt 0b No interrupt 1b Interrupt write 1 to clear 4 HP10INT R W 0b HPROT10 Interrupt 0b No interrupt 1b Interrupt write 1 to clear 3 LP...

Page 95: ...BIT NAME ACCESS RESET DESCRIPTION 7 6 VTHREF R W 00b Threshold voltage for comparators in AIO 9 6 00b 0 1V 01b 0 2V 10b 0 5V 11b 1 25V 5 DOUT5 R W 0b Data output to AIO5 4 DOUT4 R W 0b Data output to...

Page 96: ...W 0b AIO2 AIO7 buffer output select 0b Enable output buffer to AIO2 1b Enable output buffer to AIO7 6 5 AIOBUFSELIN R W 0b AIO2 AIO7 buffer input select 00b ADC VREF 01b AB4 10b AB5 11b AB6 4 AIOBUFEN...

Page 97: ...to 0 5 DIN5 R 0b Data input from AIO5 4 DIN4 R 0b Data input from AIO4 3 DIN3 R 0b Data input from AIO3 2 DIN2 R 0b Data input from AIO2 1 DIN1 R 0b Data input from AIO1 0 DIN0 R 0b Data input from A...

Page 98: ...OC CFGIO1 AIO10 AIO13 Configuration 1 1Dh BIT NAME ACCESS RESET DESCRIPTION 7 5 RFU R 000b Reserved write as 0 4 EN_AIO6_OCP RW 0b Enable AIO6 comparator output to disable gate driver on OC event 3 VR...

Page 99: ...abled 5 AIO7REINTEN R W 0b AIO7 digital input rising edge interrupt enable 0b disabled 1b enabled 4 AIO6REINTEN R W 0b AIO6 digital input rising edge interrupt enable 0b disabled 1b enabled 3 AIO9FEIN...

Page 100: ...t high 5 HP10STAT R 0b HPROT10 Real time status 0b Comparator output low 1b Comparator output high 4 LP10STAT R 0b LPROT10 Real time status 0b Comparator output low 1b Comparator output high 3 AIO9INT...

Page 101: ...nking time for BEMF Comparator 0000b 100ns 0001b 250ns 0010b 500ns 0011b 750ns 0100b 1000ns 0101b 1250ns 0110b 1500ns 0111b 2000ns 1000b 2500ns 1001b 3000ns 1010b 3500ns 1011b 4000ns 1100b 4500ns 1101...

Page 102: ...10mV 0111b Rising 5mV Falling 20mV 1000b Rising 10mV Falling 0mV 1001b Rising 10mV Falling 5mV 1010b Rising 10mV Falling 10mV 1011b Rising 10mV Falling 20mV 1100b Rising 20mV Falling 0mV 1101b Rising...

Page 103: ...CCFG0 HYSMODE 1 0000b Rising 0mV Falling 0mV 0001b Rising 0mV Falling 20mV 0010b Rising 0mV Falling 40mV 0011b Rising 0mV Falling 80mV 0100b Rising 20mV Falling 0mV 0101b Rising 20mV Falling 20mV 0110...

Page 104: ...lling 20mV 0010b Rising 0mV Falling 40mV 0011b Rising 0mV Falling 80mV 0100b Rising 20mV Falling 0mV 0101b Rising 20mV Falling 20mV 0110b Rising 20mV Falling 40mV 0111b Rising 20mV Falling 80mV 1000b...

Page 105: ...1b AB3 100b AIO8 phase to phase compare 101b AIO9 phase to phase compare 110b RFU 111b RFU 3 RFU R 0b Reserved write to 0 2 0 SMUXAIO8 R W 000b Special Mode Comparator Input MUX Selection for AIO8 000...

Page 106: ...Controller 106 Copyright 2020 Qorvo Inc Rev 1 2 Jan 17 2019 9 20 33 SOC GP0 Register 9 32 SOC GP0 General Purpose Register Space 26h BIT NAME ACCESS RESET DESCRIPTION 7 0 VAL R W 0b General purpose re...

Page 107: ...10 APPLICATION SPECIFIC POWER DRIVER 10 1 Features 3 high side gate drivers with programmable gate driving up to 1A 3 low side gate drivers with programmable gate driving up to 1A 100 duty cycle Cycle...

Page 108: ...19 10 2 System Block Diagram Figure 10 1 ASPD System Block Diagram APPLICATION SPECIFIC POWER DRIVERS HIGH SIDE GATE DRIVERS PRE DRIVER DRHx DRSx LEVEL SHIFT BBM FAULT PROTECT CURRENT LIMIT HS PORT PW...

Page 109: ...RV SOC CFGDRV1 HSPREN PB 5 3 SOC DRVILIMHS HSSOURCE CBCCTL SOC CFGDRV3 nHPxyCBCM SOC MODULE_EN nDRVFLT_MSK SOC CFGDRV2 nDRVxyDISM SOC CFGDRV2 LPCBCHS SOC CFGDRV3 nLPxyCBCM SOC STATDRV DRVxyDISSTAT SOC...

Page 110: ...DRVFLT_MSK SOC CFGDRV2 nDRVxyDISM SOC CFGDRV2 LPCBCLS SOC CFGDRV3 nLPxyCBCM SOC STATDRV DRVxyDISSTAT SOC STATDRV DRVxyDIS Smart State Machine The DRL 2 0 outputs of the ASPD are used to drive the gate...

Page 111: ...ver manager is enabled the gate drivers will be driven high or low according to the PWM inputs configured by the MCU 10 8 Driver Protection During operation the ASPD may disable the gate drivers when...

Page 112: ...n of the MCU The diagram below shows how the protection comparators can be used to generate an event signal PWMCBC which can be used to control this operation Figure 10 4 Cycle by Cycle Current Limit...

Page 113: ...sable DRH5 If CFGDRV2 LPCBCLS 1b and CFGDRV2 nDRV52DISM 1b disable DRL2 PWMCBC high If CFGDRV2 LPCBCHS 1b and CFGDRV2 nDRV41DISM 1b disable DRH4 If CFGDRV2 LPCBCLS 1b and CFGDRV2 nDRV41DISM 1b disable...

Page 114: ...SOC ENDRV DRVFLTEN to 0b then set this field to a 1b 10 11 VP UVLO Configuration If SOC CFGDRV4 VPUVLOQUAL is set to 0b then the VP UVLO threshold is set to VUVLOR VP when VP is rising and VUVLOF VP w...

Page 115: ...ivers which will be used during the miller plateau of VGS to control the slew rate The user may configure the duration of the controlled current and the current output of the gate drivers during this...

Page 116: ...The gate driver input is a PWM signal from the MCU s PWM Timer The user can configure the amount of time to apply the controlled current gate driver by setting the CFGDRV1 HS_TON_SET for the high side...

Page 117: ...s 100b 1 1 s 101b 0 9 s 110b 0 75 s 111b 0 55 s The current that is applied during this time is configurable by the user as follows High side gate driver source current DRVILIMHS HSSOURCE High side g...

Page 118: ...1 2 Jan 17 2019 Table 10 2 ASPD Controlled Current Time Configuration Register Value Time Duration DRVILIMHS HSSOURCE DRVILIMHS HSSINK DRVILIMLS LSSOURCE DRVILIMLS LSSINK 000b 250mA 001b 350mA 010b 4...

Page 119: ...OC CFGDRV2 Driver Configuration 2 00h 29h SOC CFGDRV3 Driver Configuration 3 00h 2Ah SOC STATDRV Driver Status 00h 79h SOC DRVILIMS Low side Driver Current Limit Configuration 00h 7Ah SOC DRVILIMH Hig...

Page 120: ...T R W 0x0 High side driver turn on set 000b 4 7 s 001b 2 5 s 010b 1 8 s 011b 1 3 s 100b 1 1 s 101b 0 9 s 110b 0 75 s 111b 0 55 s 4 2 LS_TON_SET R W 0x0 Low side driver turn on set 000b 4 7 s 001b 2 5...

Page 121: ...r DRH4 DRL1 high side low side or both driver disable Used for PWM pulse cycle by cycle current limit 0b not masked 1b masked 2 nDRV30DISM R W 0b Mask signal for DRH3 DRL0 high side low side or both d...

Page 122: ...or PWM pulse cycle by cycle current limit 0b masked 1b not masked 5 nHP32CBCM R W 0b Mask signal for HPROT32 for PWM pulse cycle by cycle current limit 0b masked 1b not masked 4 nLP54CBCM R W 0b Mask...

Page 123: ...ver disable inactive 1b Driver disable active 3 DRV30DISSTAT R 0b Real time status of DRV30DIS signal 0b Driver disable inactive 1b Driver disable active 2 DRV52DIS R 0b Latched status of DRV54DIS sig...

Page 124: ...ET DESCRIPTION 7 RFU R 0b Reserved write as 0b 6 4 LSSINK R W 000b Low side gate driver programmable sink current 000b 250mA 001b 350mA 010b 450mA 011b 550mA 100b 650mA 101b 750mA 110b 850mA 111b 1000...

Page 125: ...ET DESCRIPTION 7 RFU R 0b Reserved write as 0b 6 4 HSSINK R W 000b High side gate driver programmable sink current 000b 250mA 001b 350mA 010b 450mA 011b 550mA 100b 650mA 101b 750mA 110b 850mA 111b 100...

Page 126: ...by VP threshold and VP power OK threshold 0 ENBBM R W 0b Enable Break before make 0b Do not enable break before make protection 1b Enable break before make protection BIT NAME ACCESS RESET DESCRIPTIO...

Page 127: ...nager Enable 7Dh 10 15 10 SOC WDTPASS Register 10 10 SOC WDTPASS WDT Password 7Eh BIT NAME ACCESS RESET DESCRIPTION 7 1 RFU R 000 0000b Reserved write as 0 0 ENDRV RW 0b Driver Manager Enable 0b Disab...

Page 128: ...es or any other intellectual property rights whether with regard to such information itself or anything described by such information THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO TH...

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