Power Application Controller
®
-31-
Copyright 2020 © Qorvo, Inc.
Rev 1.2
– Jan 17, 2019
This allows the any VPLOW event to be captured in the latch register, even if VP returns to
normal operation. When
SOC.STATUS.VPLOW_LATCH
is set to 1b, then this bit will be
cleared and the IRQ1 signal to the MCU will be de-asserted.
As soon as VP rises above the power good threshold,
SOC.STATUS.VPLOW
will be set to 0b.
8.6
Power Manager Faults
The power manager monitors all the power supplies and LDOs for faults during operation.
During a power management fault condition such as under-voltage or over-current each of the
power supplies will set a fault bit and certain power supplies will be disabled as a result of the
fault. During all power supply faults,
SOC.ENSIG.ENSIG
,
SOC.ENDRV.ENDRV
and
SOC.MISC.MCUALIVE
are all set to 0b.
Table 8-1 Power Manager Fault Handling
FAULT
ACTION
FAULT BIT
VP
Disable VP, VSYS, VCCIO, VCORE and VCC33.
SOC.FAULT.VPFLT
VSYS
Disable VSYS, VCCIO, VCORE and VCC33
SOC.FAULT.VSYSFLT
VCCIO
Disable VCCIO, VCORE, VCC33
SOC.FAULT.VCCIOFLT
SOC.FAULT.VCOREFLT
SOC.FAULT.VCC33FLT
VCORE
Disable VCCIO, VCORE, VCC33
SOC.FAULT.VCCIOFLT
SOC.FAULT.VCOREFLT
SOC.FAULT.VCC33FLT
VCC33
Disable VCCIO, VCORE, VCC33
SOC.FAULT.VCCIOFLT
SOC.FAULT.VCOREFLT
SOC.FAULT.VCC33FLT
To reset the fault condition, the corresponding fault bit(s) should be written to a 1b and then the
power supplies will be re-started according to the power supply sequence.
8.7
Temperature Warnings and Faults
The PAC5527 monitors the device temperature for two different thresholds:
•
Temperature Warning
•
Temperature Fault
When the die temperature exceeds the temperature warning threshold of 140°C, the
SOC.FAULT.TMPWARN
bit and the
SOC.FAULT.TMPWARN_LATCH
bits are both set to 1b.
If the
SOC.FAULTEN.TMPWARNINT
bit is set to 1b (interrupt not masked), then an interrupt on
IRQ1 will be asserted to the MCU. Writing
SOC.FAULT.TMPWARN_LATCH
to 1b will reset this
bit to 0b and will de-assert the IRQ1 signal.
