Power Application Controller
®
-114-
Copyright 2020 © Qorvo, Inc.
Rev 1.2
– Jan 17, 2019
10.10 Gate Driver Short Protection
The driver manager can detect short-circuit conditions in the low-side MOSFET when enabled.
To enable this feature, set
SOC.ENDRV.DRVFLTEN
(driver fault enable) to 1b.
When the low-side gate is turned off, if the DRLx voltage does not fall below the V
SC;DRL
threshold within the t
SC;DRL
time, then a fault is declared. When the low-side gate is turned on, if
the DRLx voltage does not rise above the V
SC;DRL
threshold within the t
SC;DRL
time, then a fault is
declared.
When the fault is declared, the driver manager will be disabled and the
SOC.DRV_FLT.DRV_FLT
bit will be set to 1b and an interrupt on IRQ1 will be asserted. To
clear this condition, set
SOC.ENDRV.DRVFLTEN
to 0b then set this field to a 1b.
10.11 VP UVLO Configuration
If
SOC.CFGDRV4.VPUVLOQUAL
is set to 0b, then the VP UVLO threshold is set to V
UVLOR;VP
when VP is rising, and V
UVLOF;VP
when VP is falling.
If the
SOC.CFGDRV4.VPUVLOQUAL
is set to 1b, then the VP UVLO threshold is set as above
qualified by the VP power OK threshold. For example, when VP is rising the VP UVLO threshold
is set when VP crosses V
UVLOR;VP
and k
POKR;VP
. When VP is falling, the VP UVLO threshold is set
when VP crosses V
UVLOF;VP
and k
POKF;VP
.
10.12 Break-before-make Configuration
The PAC5527 contains support for “break-before-make” gate driver safety. When
SOC.CFGDRV4.ENBBM
is set to 1b, then the gate driver will force a 100ns dead-time in
between the half-bridge complementary gate drivers (DRH0/DRL0, DRH1/DRL1, DRH2/DRL2).
Note that this safety check is in addition to the programmable dead-time that the MCU inserts
between the high-side and low-side gate driver inputs.
