BIW1A
series
~41~
CMOS Setup Utility – Copyright © 1984 – 1998 Award Software
Advanced Chipset Features
SDRAM CAS Latency Time
3
SDRAM Cycle Time Tras/Trc
6/8
SDRAM RAS-to-CAS Delay
3
SDRAM RAS Precharge Time
3
System BIOS Cacheable
Enabled
Video BIOS Cacheable
Enabled
Memory Hole At 15M-16M
Disabled
CPU Latency Timer Disabled
Delay Transaction
Enabled
On-Chip Video Window Size
64MB
Use VGA BIOS in VBU Block Enabled
* Onboard Display Cache Setting *
Initial Display Cache Enabled
CAS# Latency
3
Paging Mode Control
Open
RAS-to-CAS Override
by CAS# LT
RAS# Timing
Fast
RAS# Precharge Timing
Fast
Item Help
Menu Level
!
↑↓←→
Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults
SDRAM CAS Latency Time
Default: 3
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
SDRAM Cycle Time Tras/Trc
Default: 6/8
Select the number of SCLKs for an access cycle. ging them.
SDRAM RAS-to-CAS Delay
Default: 3
This field lets you insert a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed.
Fast
gives
faster performance; and
Slow
gives more stable performance. This field
applies only when synchronous DRAM is installed in the system.
SDRAM RAS Precharge Time
Default: 3
If an insufficient number of cycles is allowed for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the DRAM
may fail to retain data. This field applies only when synchronous DRAM is
