Printronix 108525-001, Maintenance Manual

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2-36 P6040/P6080 Principles of Operation
2-6. Logic C3 PCBA
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continued
z. DRAM
There are 32K words (32K x 16) of DRAM on the logic C3. The 32K is divided up into two 16K
blocks decoded as RAM0 and RAM1. Each 16K word block is built by using four 16K x 4 DRAM
devices. This method of using the x4 devices yields the most space efficient way to build large
blocks of DRAM. The host DMA can only transfer data into RAM0. There are several functional
blocks that can access the DRAM. The 68000 or any bus master can access DRAM, the refresh
circuitry accesses the DRAM for refresh only, and the hammer load circuit accesses DRAM to
transfer data to the hammer drive card. RAS only refresh occurs only during program accesses, and
as such, is synchronous with the processor. Program accesses are determined from the state of the
function codes (FC0-FC2) which the processor asserts prior to the execution of a cycle. Each
DRAM memory location must be pulsed once every 4ms to remain refreshed.
68000 DRAM access with 150ns memory devices occurs with no wait states with an 10MHz 68000
clock. The hammer load circuit also accesses the DRAM starting at an address specified by the
software, then skips 64 locations and accesses the next word of data for 44 or 66 cycles for P6040 or
P6080 respectively. The most critical timing associated with the DRAM circuit originates from the
switching of the address buffers between the three functional blocks that access the DRAM.
aa. Interrupt Structure
All interrupts derived on the logic C3 are level 4 vectored interrupts due to the use of the 68901
MFP as the vectored interrupt controller. The vector register of the 68901 MFP is at address locaĆ
tion 040016H and must be loaded with 40H. Table 2-10 defines the interrupt vectors, the priority
of each interrupt, and the function of each interrupt.
Table 2-10. Logic C3 Interrupt Vectors
Priority Vector (Hex) Definition Function
Highest 4F GPIB 7
4E GPIB 6 MPU or RESYNC
4D Timer A
Receiver Buffer Full
Receiver Error
Transmit Buffer Empty
Transmit Error
Fault Summary
DMA/MATCH - Host Parallel
Interface
NSWITCH," front panel,
Auto-Baud rate
Start Bit Pulse Width
CTS (Clear to Send)
4C
4B
4A
49
47
46
43
42 Lowest
RCV. BUF. Full
RCV. Error
XMT. Error
GPIB 5
GPIB 4
XMT. BUF.
GPIB 3
GPIB 2
Timer A Paper Feed
Paper Feed
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