Printronix 108525-001, Maintenance Manual

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2-28 P6040/P6080 Principles of Operation
2-6. Logic C3 PCBA
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continued
n. Power Circuits
The power supply gen5V, GND, +30 V and -30V. Two other voltages are required that
the power supply does not generate, +12V and -12V. These voltages are derived from the +30V
and -30V available at J2 and are required for serial interface circuitry. The logic can be found on
the page with the 68901 MFP. The optical circuits (TIL111) are used to prevent erroneous control
signals from being received by the host. When the printer is powered down, the +5 volts supplying
the logic driving the RS-232 line drivers goes away long before the 30V which drives the 12V
will. If the 12V circuits do not turn off when +5V goes away, erroneous control signals (DTR,
RTS or Reverse Channel) may be generated and sent to the host.
o. Motor Controls
The ribbon motors and shuttle motor are turned on by shuttle drive enable (NSD). Paper is moved
by asserting paper drive enable (NPDE) and toggling Paper Feed 1 and 2 (PF1 and PF2). All of the
above signals are under software control.
1. Paper Movement
PF1 400C0 RESET
400C2 SET
PF2 400C4 RESET
400C6 SET
NPDE 400D4 RESET
400D6 SET
PF1 and PF2 are used in conjunction with each other to move the paper. If NPDE is not
set, paper will not move when PF1 and PF2 are switched. To move paper forward, set
NPDFE and then switch PF1 and PF2 in the following manner:
PF2 SET
PF1 SET
PF2 RESET
PF1 RESET
2. Shuttle and Ribbon Movement
NSD 400D0 RESET
400D2 SET
To make the shuttle and ribbon motors turn on, set NSD.
p. Front Panel Interface
The logic C3 front panel interface is used with the front panel defined by PCBA 107823-002 and is
not backward compatible to the logic C2, C1 or A and B board sets. Signals to the front panel inĆ
clude: NENABLE, NPLOAD, PDATA (bidirectional), NPCLK, and REGSEL. Signals from the
front panel include NSWITCH and NPFAULT. NPCLK is used in conjunction with PDATA to
clock the serial data stream into or out of the front panel.
NPCLOCK is the anded combination of front panel data write (NFPDATAW) and panel clock
(PCLK). The NPCLK signal is active when PCLK is reset and NFPDATAW is written to. Note that
Panel Load (PLOAD) must be set when the data is shifted out to the panel.
The front panel switches and three fault status lines can be read as a single eight-bit word any time
by software using the steps following:
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