Printronix 108525-001, Maintenance Manual

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2-31 P6040/P6080 Principles of Operation
2-6. Logic C3 PCBA
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continued
s. Control Signals
The control signals to and from the processor control the bus activity on the card. Several of the
control signals on the 68000 are unused. The unused signals include: VPA, VMA, BERR, and E (1
MHz clock).
1. CPU Bus Control Signals
The control signals on the bus that are controlled by the 68000 include: NAS, R/NW,
NUDS and NDTACK (N denotes active low).
NAS
Active low signal that asserts 70ns (min.) after the address that 68000 MPU
put on the bus stabilize.
R/NW When high, the processor reads from the data bus. When low, the processor
writes to the data bus.
NUDS Asserts low when the data on the upper data bus is valid (D8-D15).
NLDS Asserts low when the data on the lower data bus is valid (D0-D7).
NDTACK Sampled by the processor to determine if the peripheral that was addressed
has received the information that was sent to it. Until this signal goes low, the
processor will wait with the address and data busses asserted.
2. Bus Arbitration Control Signals
The bus arbitration signals include: NBG, NBR and NBGACK. Presently, the 68B44 is
the only device on the C3 card that asserts the bus request (NBR) and grant acknowledge
(NBGACK) signals. The bus arbitration signals are available at the expansion connector.
Note that the PAL decode logic takes the positive true BGACK signal from the circuitry
around the 68B44 and decodes the space of RAM0. The NBGACK signal from the expanĆ
sion connector does not effect this decode logic. Both the NBR and NBGACK signals into
the 68000 are open collector.
3. Interrupt Control Signals
The signals used for the interrupt processing include IPL0, IPL1, IPL 2, FC0, FC1 and
FC2. The C3 card uses only the IPL2 line, or level four interrupt. All three of the interrupt
request lines (IPLX) go to the expansion connector and are open collector lines. In reĆ
sponse to an interrupt, the function code lines (FCX) all assert high. The function codes,
when in interrupt mode, disable the address decode circuitry.
When all of the function codes are high in the interrupt acknowledge cycle, the NCIACK
line that interfaces to the 68901 MFP goes active low. At this time the MFP puts the vector
of the interrupt on the lower data bus for the processor to read. When the MFP asserts
NDTACK, the 68000 latches the data and negates NUDS and NLDS, completing the inĆ
terrupt acknowledge cycle.
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