Printronix 108525-001, Maintenance Manual

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2-23 P6040/P6080 Principles of Operation
2-6. Logic C3 PCBA
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continued
g. Host Interfaces
All three of the popular interfacing formats are available on the Logic C3. Only one can be active
at a time, and different cables must be installed in order to activate each particular interface.
There is one header associated with the host interface, located at 6A on the logic C3, the header
must be installed per the logic C3 configuration drawing (108078). The use of the header allows
both the parallel and serial data to be received with the same device, a 75154. These devices have
adjustable hysteresis allowing the reception of RS-232 or TTL signal levels based on the voltage
to the hysteresis control pin of each receiver.
h. Serial Interface
The serial interface is handled through a UART that resides within the 68901 MFP. A 2.4576 MHz
clock into the device allows for internally generated baud rates of up to 19.2K. The available baud
rates include: 19.2K, 9.6K, 4.8K, 2.4K, 1.2K, 600, 300, 150, 110, 100, 75 and 50 baud. Timer C genĆ
erates the clock for the baud rates.
Several options are available for clocking in the serial data stream. The RS-232 interface has
three clock lines, all of which are jumperable to the transmit clock (TC) or receive clock (RC) pins
on the 68901. The three clock lines at the interface are Transmit Clock (NTXCLK), receive clock
(NRXCLK), and external clock (NEXTCLK). The etch is configured so that the timer C output is
the controlling clock to the TC and RC pins of the 68901. Any of the RS-232 inputs are available
to the UART provided the proper etch cuts and jumpers are made.
The option for auto baud rate configuration is available. The timer B input pin (TBI) is tied to the
receive data (RXD) line so that in an auto configuration mode, the software driving the 68901
could determine the baud rate of the incoming data stream, and set up timer C accordingly.
RS-232 control signals are also handled through the UART in the 68901. Data carrier detect
(NDCD) and data set ready (NDSR) are anded together and routed to one of the status port lines.
Clear to Send (CTS) is routed to the 68901 GPIB2. Transitions on these pins cause serial processĆ
ing to begin. The software response to the transition will cause the assertion of some combination
of the interface response lines. The response lines include: request to send (RTS), data terminal
ready (DTR) and reverse channel. These lines are controlled by software. DTR and RTS originate
from the 68901 general purpose I/O ports GPIB1 and GPIB0. Reverse channel is asserted by writĆ
ing to a software setable latch at hex address 040152 and reset by writing to 040150.
i. Parallel Interfaces
Both the Centronics and Dataproducts parallel interfaces are available to the user. The selection
of the interface used is based solely on the cable that is plugged into the printer during interface
configuration.
The parallel interface required to run at rates of 500 kb/s in Dataproducts mode uses a DMA conĆ
troller to permit the high speed transfer of the parallel data stream into the DRAM. The DMA
used is a 68B44, a 2 MHz device that arbitrates for the bus on every character that it sends into the
DRAM.
After an NMC is asserted (RESET), several operations must occur before data reception can be
enabled. To ensure that no data transfers take place during the parallel port initialization, ONL
and RDY control signals must not be asserted.
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