Rev. A 10/18
28
Application Note
AN-72
www.power.com
Recommendations to Reduce No-load Consumption
The InnoSwitch3 IC will start in self-powered mode, drawing energy
from the BYPASS pin capacitor that is charged from an internal
current source. A bias winding is required to provide supply current
to the PRIMARY BYPASS pin once the InnoSwitch3 IC has started
switching. A bias winding supply to the PRIMARY BYPASS pin enables
power supplies with no-load power consumption of less than 15 mW.
Resistor R
BP
shown in Figure 13 should be adjusted to achieve the
lowest no-load input power.
Other areas that may help reduce no-load consumption further
are;
1. Low value of primary clamp capacitor, C
SN
.
2. Schottky or ultrafast diode for bias supply rectifier, D
BIAS
.
3. Low ESR capacitor for bias supply filter capacitor, C
BIAS
.
4. Low value SR FET RC snubber capacitor, C
SR
.
5. Tape between primary winding layers, and multi-layer tapes
between primary and secondary windings to reduce inter
winding capacitance.
Recommendations for Reducing EMI
1. Appropriate component placement and small loop areas of the
primary and secondary power circuits help minimize radiated
and conducted EMI. Care should be taken to achieve a compact
loop area. (See Figures 19 and 20)
2. A small capacitor parallel to the clamp diode on the primary-side
can help reduce radiated EMI.
3. A resistor (2 – 47
Ω
) in series with the bias winding helps reduce
radiated EMI.
4. A small resistor and ceramic capacitor (< 22 pf) in series across
primary shown in Figure 20 and/or across secondary winding
(< 100 pf) may help reduce conducted and/or radiated EMI.
However if value is large, then no-load consumption will
increase.
5. Common mode chokes are typically required at the input of the
power supply to sufficiently attenuate common-mode noise.
However, the same performance can be achieved by use of
shield windings in the transformer. Shield windings can also be
used in conjunction with common mode filter inductors at the
input to reduce conducted and radiated EMI.
6. Adjusting SR MOSFET RC snubber component values can help
reduce high frequency radiated and conducted EMI.
7. A pi filter comprising differential inductors and capacitors can be
used in the input rectifier circuit to reduce low frequency
differential EMI. A ferrite bead as shown in Figure 20 can be
added to further improve EMI margin at minimal cost.
8. A resistor across the differential inductors reduces their Q factor
which can reduce EMI above 10 MHz. However low frequency
EMI below 5 MHz may increase slightly.
9. A 1
µ
F ceramic capacitor connected at the output of the power
supply may help to reduce radiated EMI.
10. A slow diode (i.e. 250 ns < t
RR
< 500 ns) as the bias rectifier
(D
BIAS
) is generally good for reducing conducted EMI > 20 MHz
and radiated EMI
> 30 MHz.
Recommendations for Increased ESD Immunity
1. Sufficient clearance should be maintained (> 8 mm) between the
primary-side and secondary-side circuits (especially underneath
InSOP package and transformer).
a. It is not recommended to place spark gap near or
across InSOP package.
2. Use two spark gaps connected to secondary terminals (output
return and positive) and one of the AC inputs after the fuse
(see Figure 21). In this configuration at least 5.4 mm gap is
often sufficient to meet creepage and clearance requirements of
applicable safety standards.
a. For applications with a USB connector, float the PCB pads
connected to the legs of the connector.
3. Use a spark gap across common-mode choke or inductor to
provide a low impedance path for any high energy discharge
build up due to ESD or common mode surge.
4. Use a Y capacitor connected from either positive or negative
output terminals to the input bulk capacitor’s positive terminal or
to the AC input after the fuse.
5. Employ good layout practices and follow the PCB layout
recommendations in the application note.
6. Apply multi-layer tape between bias and secondary windings,
and also between secondary and primary windings.
Thermal Management Considerations
The SOURCE pin is internally connected to the IC lead frame and
provides the main path to remove heat from the device. Therefore
the SOURCE pin should be connected to a copper area underneath
the IC to act not only as a single point ground, but also as a heat
sink. As this area is connected to the quiet source node, it can be
maximized for good heat sinking without causing EMI proplems.
Similarly for the output SR MOSFET, maximize the PCB area
connected to the pins on the package through which heat is
dissipated.
Sufficient copper area should be provided on the board to keep the
IC temperature safely below absolute maximum limits. It is
recommended that the copper area to which the SOURCE pin of the
IC is soldered is sufficiently large to keep the IC temperature below
90 °C when operating the power supply at full rated load and at the
lowest rated input AC supply voltage (at nominal ambient). Further
de-rating can be applied as required.
Heat Spreader
For stringent thermal requirements, position the IC adjacent to the
transformer as shown in Figure 23-d. This will reduce heat transfer
to the IC from the transformer. For enclosed high power applications
such as laptop adaptor or similar applications with high ambient
environment, using the PCB as a heat sink may not be enough for the
IC to operate within specified operating temperature, therefore a
metal heat spreader may be necessary to keep the IC cool. Unless a
ceramic material is used for the heat sink, care must be taken to
maximize the safety limit. A heat spreader is formed by combination of
a heat spreader material (Copper or Aluminum), a 0.4 mm mylar pad
(for reinforced isolation) and a thermally conductive pad for better
heat transfer between the IC and the spreader.
Figure 24 shows the basic idea how to implement the attachment of a
heat spreader to an InSOP-24D package while maintaining creepage
between primary-side and secondary-side pins of InnoSwitch3 IC.