Rev. A 10/18
25
Application Note
AN-72
www.power.com
Layout Example
Figure 21. TOP and BOTTOM Sides – Ideal Layout Example Showing Tight Loop Areas for Circuit with High dv/dt or di/dt, Component Placement and Spark-Gap
Location in Reference to Figures 19 and 20.
Special Notes
• All loops are separated; no loop is inside a loop. This will avoid ground impedance noise coupling.
•
Keep trace surface area and length of high dv/dt nodes such as Drain, as small and short as possible to minimize RFI generation.
•
No (quiet) signal trace such as Y capacitor and feedback return should be routed near to or across noisy nodes (high dv/dt or di/dt) such as Drain, underneath
transformer belly, switching-side of any winding or output rectifier diode. This avoids capacitive or magnetic noise coupling.
•
No signal trace should share path with traces having an AC switching current such as the output capacitors. Connection must be star-connected to capacitor
pad in order to avoid ground impedance coupled noise.
PI-8522-091318
Primary loop (1) formed
by C2, NP and D-S pin is
compact and small
Optional Y capacitor
connected to RTN
and C1 (+)
Note that Drain trace is
short and narrow
5.5 mm spark-gap; primary-side
is connected directly to the AC input (after the fuse),
while secondary-side has one from RTN and VOUT
to increase effectiveness
Output loop (5) formed
by CPF, RIS and COUT
does not share ground
path with secondary
loop (4)
Secondary loop (4)
formed by NS, COUT
and SR FET is compact
and small
Components CBPS,
CFB, RLS1, RFBLOWER
and GND pin share one
ground path that is
star-connected to RIS
All signal components
are placed as close as
possible to IC pin via
short traces
No trace is routed
underneath the IC to
increase ESD immunity
Components CBPP, RBP, RLS1 and
RLS are placed as close as possible
to IC pin to which they are
connected to with short traces
Bias supply loop (3)
formed by NB, DBIAS and
CBIAS is compact and small
Copper heat sink for
SOURCE pin is
maximized
LF, C1 and FB are
positioned away from
any switching nodes
with high di/dt or dv/dt
Primary clamp loop
area (2) formed by
CSN, RS, DSN and
NP is compact and small
1
5
4
3