PLX Technology PEX 8618, Quick Start Manual

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PEX 8618 Quick Start Hardware Design Guide – Version 1.2
Copyright © 2009 by PLX Technology, Inc. All rights reserved.
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Figures
Figure 1. Sample PCI Express Link Block Diagram .................................................................................. 1
Figure 2. Single-Ended versus Differential Voltage .................................................................................. 2
Figure 3. Transport Delay Delta ................................................................................................................ 5
Figure 4. PEX 8618 RefClk Circuit ............................................................................................................ 5
Figure 5. Single Reference Clock Scheme (STRAP_SSC_ISO_ENABLE# pulled high) ......................... 6
Figure 6. Dual Reference Clock; SSC Crossing Scheme (STRAP_SSC_ISO_ENABLE# pulled low) ..... 7
Figure 7. Add-In Card Routing to PCI Express Gold Fingers ................................................................... 9
Figure 8. System Board Routing to PCI Express Slot ............................................................................... 9
Figure 9. PCI Express Midbus Routing Example .................................................................................... 10
Figure 10. Enable NT Function with NT Strapping Balls ......................................................................... 11
Figure 11. Disable NT Function .............................................................................................................. 11
Figure 12. SHPC Interface to PEX 8618 Block Diagram ........................................................................ 12
Figure 13. JTAG Interface Block Diagram .............................................................................................. 13
Figure 14. I
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C Interface Block Diagram .................................................................................................. 14
Figure 15. Power Plane Impedance versus Frequency .......................................................................... 19
Figure 16. Capacitor Footprint Effects on Series Inductance ................................................................. 20
Tables
Table 1. Receiver Equalization Settings ................................................................................................... 4
Table 2. Cross-Reference of Ball Names and Related Debug Signal Names ........................................ 15
Table 3. Strapping Balls .......................................................................................................................... 17