Figure 6
demonstrates a mixed SSC and CFC system that might exist when utilizing PEX 8618’s SSC isolation
feature. NOTE: When SSC isolation is used, the SSC clock must be connected to PEX_REFCLKp/n.
PEX 8618
Port 0
Port 1
. . .
Port N
VSS
PEX _REFCLK _CFCp
/n
PEX _REFCLKp
/n
Spread Spectrum Clock
( SSC)
Constant Frequency Clock
( CFC) environment
Upstream
Downstream
Device
Downstream
Device
1
RefClk
Generator
REFCLKp
/n
REFCLKp /n
(Not required to be rom
f
same source
)
2
RefClk
STRAP_SSC_ISO_ENABLE#
Generator
Device
Figure 6. Dual Reference Clock; SSC Crossing Scheme (STRAP_SSC_ISO_ENABLE# pulled low)
1.5
Channel
In PCI Express, the channel refers to the board level copper interconnects (including connectors) that lie between
the Transmitter and Receiver balls. The channel is represented as a transmission line, which can be modeled by
a distributed series of Resistance Inductance Conductance Capacitance (RLGC) circuits. A transmission line
behaves like a low-pass filter due to frequency-dependent dielectric and conductor losses.
In PCI Express, the channel contributes to amplitude loss and deterministic jitter. It is important to minimize
discontinuities,
such as
vias and stubs, to minimize channel effects.
A common issue that presents itself to PCI Express system designers is determining allowable channel length.
This is a question that does not have a simple answer. The best way to determine if a particular channel length is
allowable is to simulate the channel using PLX provided HSPICE models. The
PCI Express Base Specification,
Revision 2.0
provides additional details for simulating a channel.
PEX 8618 Quick Start Hardware Design Guide – Version 1.2
Copyright © 2009 by PLX Technology, Inc. All rights reserved.
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