PEX 8618 Quick Start Hardware Design Guide – Version 1.2
Copyright © 2009 by PLX Technology, Inc. All rights reserved.
18
10
Power Supplies, Sequencing, and De-Coupling
The switch’s maximum power consumption is approximately 4.5W. Special cooling requirements may exist,
depending upon the system environment. (Refer to the
PEX 8618 Data Book
for details).
10.1 Power Supplies
The PEX 8618 has the following Power ball groups:
VDD10 – Digital core logic supply
VDD10A – SerDes analog supply
VDD25 – Hot-Plug, serial EEPROM, I
2
C, JTAG, Port Status indicators, I/O buffers
VDD25A – PEX_REFCLK PLL supply
At the board level, VDD10 and VDD10A can share a common 1.0V ±5% power plane, and VDD25 and VDD25A
can share a common 2.5V power plane. The current demands for these supplies can be high, depending upon
the device (approximately 80 mA per Lane, plus 32 mA); therefore, ensure that the power plane is sufficiently
sized, to support the specified operating current. See section
below for details on power supply de-coupling.
VDD10A has a lower noise tolerance than the digital supplies. Therefore, VDD10A might require additional
filtering, depending upon the 1.0V ±5% power plane noise. The SerDes can tolerate ±5% variance on the supply
rails, due to noise and IR drop. VDD25 power is used for the single-ended I/O buffers – Hot-Plug, serial
EEPROM, JTAG, I
2
C, and the Port Status indicators. Although power consumption for this supply is relatively
small, the output drivers have fast edge rates, and therefore, require that adequate power de-coupling be provided,
to supply transient current to the drivers. It is preferred that VDD25 be implemented as a plane or partial plane,
either on a signal layer or main power plane layer. Provide 0.1 and/or 0.01 µF ceramic capacitors, along with
one or more 10-µF tantalum capacitors, to de-couple the VDD25 power balls. The number of capacitors required
depends upon the number of 2.5V I/O balls utilized in the design, and the existence or absence of an interplane
capacitance for the VDD25 rail.
VDD25A (and VSSA_PLL) are used to power the internal Reference Clock PLL. This ball might require additional
filtering circuitry, if the VDD25 plane is experiencing significant noise. VDD25A can tolerate ripple from -100 to
+100 mV, for frequencies above 10 MHz. If additional filtering circuitry is necessary, a wide trace (0.254 to
0.381 mm; 0.010 to 0.015 in.) can be used to power this supply ball. Use a 0-ohm resistor (0603 or 0805), in
series with the main VDD25 supply, along with one or more 0.1 and/or 0.01 µF capacitors after the resistor, near
the ball. If the VDD25 plane couples significant noise into the VDD25A supply, exchange the resistor for a ferrite
bead, to aid in filtering the supply noise. In designs where VDD25A ties directly to the VDD25 power plane,
ensure that VDD25A has its own dedicated via to the plane. Similarly, allow VSSA_PLL to have its own dedicated
via to the main ground plane.
Note: Placing ferrite beads in a power supply path is not a preferred method of filtering noise for supply rails.
Power supplies isolated through the use of ferrite beads typically have limited access to interplane capacitance,
which might have an adverse effect on a given supply rail.
10.2 Power Sequencing
There is no power sequencing requirement.
